nir/vtn: SPIR-V bit count opcodes (core and extension) dest size mismatches nir

[mesa.git] / src / panfrost / midgard / midgard_compile.h

diff --git a/src/panfrost/midgard/midgard_compile.h b/src/panfrost/midgard/midgard_compile.h
index f76715e7a537b81c676fc0e415f27c8d5a9e38c4..850e72641e7fc970039b9b80ecb0a935c5bda656 100644 (file)
--- a/src/panfrost/midgard/midgard_compile.h
+++ b/src/panfrost/midgard/midgard_compile.h
@@ -26,90 +26,10 @@
 
 #include "compiler/nir/nir.h"
 #include "util/u_dynarray.h"
-#include "util/register_allocate.h"
-
-/* To be shoved inside panfrost_screen for the Gallium driver, or somewhere
- * else for Vulkan/standalone. The single compiler "screen" to be shared across
- * all shader compiles, used to store complex initialization (for instance,
- * related to register allocation) */
-
-struct midgard_screen {
-        /* Precomputed register allocation sets for varying numbers of work
-         * registers.  The zeroeth entry corresponds to 8 work registers. The
-         * eighth entry corresponds to 16 work registers. NULL if this set has
-         * not been allocated yet. */
-
-        struct ra_regs *regs[9];
-
-        /* Work register classes corresponds to the above register sets */
-        unsigned reg_classes[9][4];
-};
-
-/* Define the general compiler entry point */
-
-#define MAX_SYSVAL_COUNT 32
-
-/* Allow 2D of sysval IDs, while allowing nonparametric sysvals to equal
- * their class for equal comparison */
-
-#define PAN_SYSVAL(type, no) (((no) << 16) | PAN_SYSVAL_##type)
-#define PAN_SYSVAL_TYPE(sysval) ((sysval) & 0xffff)
-#define PAN_SYSVAL_ID(sysval) ((sysval) >> 16)
-
-/* Define some common types. We start at one for easy indexing of hash
- * tables internal to the compiler */
-
-enum {
-        PAN_SYSVAL_VIEWPORT_SCALE = 1,
-        PAN_SYSVAL_VIEWPORT_OFFSET = 2,
-        PAN_SYSVAL_TEXTURE_SIZE = 3,
-} pan_sysval;
-
-#define PAN_TXS_SYSVAL_ID(texidx, dim, is_array)          \
-       ((texidx) | ((dim) << 7) | ((is_array) ? (1 << 9) : 0))
-
-#define PAN_SYSVAL_ID_TO_TXS_TEX_IDX(id)        ((id) & 0x7f)
-#define PAN_SYSVAL_ID_TO_TXS_DIM(id)            (((id) >> 7) & 0x3)
-#define PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(id)       !!((id) & (1 << 9))
-
-typedef struct {
-        int work_register_count;
-        int uniform_count;
-        int uniform_cutoff;
-
-        int attribute_count;
-        int varying_count;
-
-        /* Prepended before uniforms, mapping to SYSVAL_ names for the
-         * sysval */
-
-        unsigned sysval_count;
-        unsigned sysvals[MAX_SYSVAL_COUNT];
-
-        unsigned varyings[32];
-
-        /* Boolean properties of the program */
-        bool writes_point_size;
-
-        int first_tag;
-
-        struct util_dynarray compiled;
-
-        /* For a blend shader using a constant color -- patch point. If
-         * negative, there's no constant. */
-
-        int blend_patch_offset;
-
-        /* The number of bytes to allocate per-thread for Thread Local Storage
-         * (register spilling), or zero if no spilling is used */
-        unsigned tls_size;
-
-        /* IN: For a fragment shader with a lowered alpha test, the ref value */
-        float alpha_ref;
-} midgard_program;
+#include "panfrost/util/pan_ir.h"
 
 int
-midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midgard_program *program, bool is_blend);
+midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb, bool silent);
 
 /* NIR options are shared between the standalone compiler and the online
  * compiler. Defining it here is the simplest, though maybe not the Right
@@ -117,8 +37,8 @@ midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midga
 
 static const nir_shader_compiler_options midgard_nir_options = {
         .lower_ffma = true,
-        .lower_sub = true,
         .lower_scmp = true,
+        .lower_flrp16 = true,
         .lower_flrp32 = true,
         .lower_flrp64 = true,
         .lower_ffract = true,
@@ -128,6 +48,7 @@ static const nir_shader_compiler_options midgard_nir_options = {
         .lower_isign = true,
         .lower_fpow = true,
         .lower_find_lsb = true,
+        .lower_fdph = true,
 
         .lower_wpos_pntc = true,
 
@@ -135,14 +56,27 @@ static const nir_shader_compiler_options midgard_nir_options = {
          * eventually */
         .lower_fsign = true,
 
-        .vertex_id_zero_based = true,
         .lower_extract_byte = true,
         .lower_extract_word = true,
         .lower_rotate = true,
 
+        .lower_pack_half_2x16 = true,
+        .lower_pack_unorm_2x16 = true,
+        .lower_pack_snorm_2x16 = true,
+        .lower_pack_unorm_4x8 = true,
+        .lower_pack_snorm_4x8 = true,
+        .lower_unpack_half_2x16 = true,
+        .lower_unpack_unorm_2x16 = true,
+        .lower_unpack_snorm_2x16 = true,
+        .lower_unpack_unorm_4x8 = true,
+        .lower_unpack_snorm_4x8 = true,
+        .lower_pack_split = true,
+
         .lower_doubles_options = nir_lower_dmod,
 
+        .lower_bitfield_extract_to_shifts = true,
         .vectorize_io = true,
+        .use_interpolated_input_intrinsics = true
 };
 
 #endif