midgard_instruction ins = {
.type = TAG_TEXTURE_4,
.mask = mask_of(nr_components),
- .dest = nir_dest_index(ctx, &instr->dest.dest),
- .src = { nir_alu_src_index(ctx, &instr->src[0]), ~0, ~0, ~0 },
+ .dest = nir_dest_index(&instr->dest.dest),
+ .dest_type = nir_type_float32,
+ .src = { ~0, nir_src_index(ctx, &instr->src[0].src), ~0, ~0 },
+ .swizzle = SWIZZLE_IDENTITY_4,
+ .src_types = { nir_type_float32, nir_type_float32 },
.texture = {
.op = mir_derivative_op(instr->op),
.format = MALI_TEX_2D,
}
};
- ins.swizzle[0][2] = ins.swizzle[0][3] = COMPONENT_X;
- ins.swizzle[1][2] = ins.swizzle[1][3] = COMPONENT_X;
-
if (!instr->dest.dest.is_ssa)
ins.mask &= instr->dest.write_mask;
emit_mir_instruction(ctx, ins);
-
- /* TODO: Set .cont/.last automatically via dataflow analysis */
- ctx->texture_op_count++;
}
void
/* Insert the new instruction */
mir_insert_instruction_before(ctx, mir_next_op(ins), dup);
- /* TODO: Set .cont/.last automatically via dataflow analysis */
- ctx->texture_op_count++;
-
/* We'll need both instructions to write to the same index, so
* rewrite to use a register */