midgard_instruction not = {
.type = TAG_ALU_4,
.mask = ins->mask,
- .src = { temp, ~0, ~0 },
+ .src = { temp, ~0, ~0, ~0 },
+ .swizzle = SWIZZLE_IDENTITY,
.dest = ins->dest,
.has_inline_constant = true,
.alu = {
/* TODO: i16 */
.reg_mode = midgard_reg_mode_32,
.dest_override = midgard_dest_override_none,
- .outmod = midgard_outmod_int_wrap,
- .src1 = vector_alu_srco_unsigned(blank_alu_src),
- .src2 = vector_alu_srco_unsigned(zero_alu_src)
+ .outmod = midgard_outmod_int_wrap
},
};
if (ins->alu.op != midgard_alu_op_imov) continue;
if (!ins->invert) continue;
if (mir_nontrivial_source2_mod_simple(ins)) continue;
- if (ins->src[1] & IS_REG) continue;
+ if (ins->src[1] & PAN_IS_REG) continue;
/* Is it beneficial to propagate? */
if (!mir_single_use(ctx, ins->src[1])) continue;
}
}
+static bool
+mir_is_inverted_bitwise(midgard_instruction *ins)
+{
+ switch (ins->alu.op) {
+ case midgard_alu_op_inand:
+ case midgard_alu_op_inor:
+ case midgard_alu_op_inxor:
+ return true;
+ default:
+ return false;
+ }
+}
+
static midgard_alu_op
mir_invert_op(midgard_alu_op op)
{
switch (op) {
case midgard_alu_op_iand:
return midgard_alu_op_inand;
+ case midgard_alu_op_inand:
+ return midgard_alu_op_iand;
case midgard_alu_op_ior:
return midgard_alu_op_inor;
+ case midgard_alu_op_inor:
+ return midgard_alu_op_ior;
case midgard_alu_op_ixor:
return midgard_alu_op_inxor;
+ case midgard_alu_op_inxor:
+ return midgard_alu_op_ixor;
default:
unreachable("Op not invertible");
}
mir_foreach_instr_in_block_safe(block, ins) {
/* Search for inverted bitwise */
if (ins->type != TAG_ALU_4) continue;
- if (!mir_is_bitwise(ins)) continue;
+ if (!mir_is_bitwise(ins) && !mir_is_inverted_bitwise(ins)) continue;
if (!ins->invert) continue;
ins->alu.op = mir_invert_op(ins->alu.op);
static bool
mir_strip_inverted(compiler_context *ctx, unsigned node)
{
- if (node >= SSA_FIXED_MINIMUM)
+ if (node == SSA_FIXED_REGISTER(26))
return false;
/* Strips and returns the invert off a node */
static bool
is_ssa_or_constant(unsigned node)
{
- return !(node & IS_REG) || (node == SSA_FIXED_REGISTER(26));
+ return !(node & PAN_IS_REG) || (node == SSA_FIXED_REGISTER(26));
}
bool
/* Search for inverted bitwise */
if (ins->type != TAG_ALU_4) continue;
if (!mir_is_bitwise(ins)) continue;
- if (ins->invert) continue;
if (!is_ssa_or_constant(ins->src[0])) continue;
if (!is_ssa_or_constant(ins->src[1])) continue;
mir_foreach_instr_in_block_safe(block, ins) {
if (ins->type != TAG_ALU_4) continue;
if (!OP_IS_CSEL(ins->alu.op)) continue;
+ if (!is_ssa_or_constant(ins->src[2])) continue;
if (!mir_single_use(ctx, ins->src[2])) continue;
if (!mir_strip_inverted(ctx, ins->src[2])) continue;
return progress;
}
+
+
+static bool
+mir_is_inverted(compiler_context *ctx, unsigned node)
+{
+ mir_foreach_instr_global(ctx, ins) {
+ if (ins->compact_branch) continue;
+ if (ins->dest != node) continue;
+
+ return ins->invert;
+ }
+
+ unreachable("Invalid node passed");
+}
+
+
+
+/* Optimizes comparisions which invert both arguments
+ *
+ *
+ * ieq(not(a), not(b)) = ieq(a, b)
+ * ine(not(a), not(b)) = ine(a, b)
+ *
+ * This does apply for ilt and ile if we flip the argument order:
+ * Proofs below provided by Alyssa Rosenzweig
+ *
+ * not(x) = −(x+1)
+ *
+ * ( not(A) <= not(B) ) <=> ( −(A+1) <= −(B+1) )
+ * <=> ( A+1 >= B+1)
+ * <=> ( B <= A )
+ *
+ * On unsigned comparisons (ult / ule) we can perform the same optimization
+ * with the additional restriction that the source registers must
+ * have the same size.
+ *
+ * TODO: We may not need them to be of the same size, if we can
+ * prove that they are the same after sext/zext
+ *
+ * not(x) = 2n−x−1
+ *
+ * ( not(A) <= not(B) ) <=> ( 2n−A−1 <= 2n−B−1 )
+ * <=> ( −A <= −B )
+ * <=> ( B <= A )
+ */
+bool
+midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block)
+{
+
+ bool progress = false;
+
+ mir_foreach_instr_in_block_safe(block, ins) {
+ if (ins->type != TAG_ALU_4) continue;
+ if (!OP_IS_INTEGER_CMP(ins->alu.op)) continue;
+
+ if ((ins->src[0] & PAN_IS_REG) || (ins->src[1] & PAN_IS_REG)) continue;
+ if (!mir_single_use(ctx, ins->src[0]) || !mir_single_use(ctx, ins->src[1])) continue;
+
+ bool a_inverted = mir_is_inverted(ctx, ins->src[0]);
+ bool b_inverted = mir_is_inverted(ctx, ins->src[1]);
+
+ if (!a_inverted || !b_inverted) continue;
+ if (OP_IS_UNSIGNED_CMP(ins->alu.op) && mir_srcsize(ins, 0) != mir_srcsize(ins, 1)) continue;
+
+
+ mir_strip_inverted(ctx, ins->src[0]);
+ mir_strip_inverted(ctx, ins->src[1]);
+
+ if (ins->alu.op != midgard_alu_op_ieq && ins->alu.op != midgard_alu_op_ine)
+ mir_flip(ins);
+
+ progress |= true;
+ }
+
+ return progress;
+}
+
+/* Optimizes branches with inverted arguments by inverting the
+ * branch condition instead of the argument condition.
+ */
+bool
+midgard_opt_invert_branch(compiler_context *ctx, midgard_block *block)
+{
+ bool progress = false;
+
+ mir_foreach_instr_in_block_safe(block, ins) {
+ if (ins->type != TAG_ALU_4) continue;
+ if (!midgard_is_branch_unit(ins->unit)) continue;
+ if (!ins->branch.conditional) continue;
+ if (ins->src[0] & PAN_IS_REG) continue;
+
+ if (mir_strip_inverted(ctx, ins->src[0])) {
+ ins->branch.invert_conditional = !ins->branch.invert_conditional;
+
+ progress |= true;
+ }
+ }
+
+ return progress;
+}
projects / mesa.git / blobdiff