#define WORK_STRIDE 10
+/* We have overlapping register classes for special registers, handled via
+ * shadows */
+
+#define SHADOW_R27 17
+#define SHADOW_R28 18
+#define SHADOW_R29 19
+
/* Prepacked masks/swizzles for virtual register types */
static unsigned reg_type_to_mask[WORK_STRIDE] = {
0xF, /* xyzw */
int phys = virt / WORK_STRIDE;
int type = virt % WORK_STRIDE;
+ /* Apply shadow registers */
+
+ if (phys >= SHADOW_R27 && phys <= SHADOW_R29)
+ phys += 27 - SHADOW_R27;
+
struct phys_reg r = {
.reg = phys,
.mask = reg_type_to_mask[type],
* work registers, although it is also used to create the register set for
* special register allocation */
+static void
+add_shadow_conflicts (struct ra_regs *regs, unsigned base, unsigned shadow)
+{
+ for (unsigned a = 0; a < WORK_STRIDE; ++a) {
+ unsigned reg_a = (WORK_STRIDE * base) + a;
+
+ for (unsigned b = 0; b < WORK_STRIDE; ++b) {
+ unsigned reg_b = (WORK_STRIDE * shadow) + b;
+
+ ra_add_reg_conflict(regs, reg_a, reg_b);
+ ra_add_reg_conflict(regs, reg_b, reg_a);
+ }
+ }
+}
+
static struct ra_regs *
create_register_set(unsigned work_count, unsigned *classes)
{
classes[4*c + 2] = work_vec3;
classes[4*c + 3] = work_vec4;
- /* Special register classes have two registers in them */
- unsigned count = (c == REG_CLASS_WORK) ? work_count : 2;
+ /* Special register classes have other register counts */
+ unsigned count =
+ (c == REG_CLASS_WORK) ? work_count :
+ (c == REG_CLASS_LDST27) ? 1 : 2;
+ /* We arbitraily pick r17 (RA unused) as the shadow for r27 */
unsigned first_reg =
- (c == REG_CLASS_LDST) ? 26 :
- (c == REG_CLASS_TEX) ? 28 : 0;
+ (c == REG_CLASS_LDST) ? 26 :
+ (c == REG_CLASS_LDST27) ? SHADOW_R27 :
+ (c == REG_CLASS_TEXR) ? 28 :
+ (c == REG_CLASS_TEXW) ? SHADOW_R28 :
+ 0;
/* Add the full set of work registers */
for (unsigned i = first_reg; i < (first_reg + count); ++i) {
}
}
+
+ /* We have duplicate classes */
+ add_shadow_conflicts(regs, 27, SHADOW_R27);
+ add_shadow_conflicts(regs, 28, SHADOW_R28);
+ add_shadow_conflicts(regs, 29, SHADOW_R29);
+
/* We're done setting up */
ra_set_finalize(regs, NULL);
if (class == current_class)
return;
+
+ if ((current_class == REG_CLASS_LDST27) && (class == REG_CLASS_LDST))
+ return;
+
/* If we're changing, we must not have already assigned a special class
*/
- assert(current_class == REG_CLASS_WORK);
- assert(REG_CLASS_WORK == 0);
+ bool compat = current_class == REG_CLASS_WORK;
+ compat |= (current_class == REG_CLASS_LDST) && (class == REG_CLASS_LDST27);
+
+ assert(compat);
+ classes[node] &= 0x3;
classes[node] |= (class << 2);
}
+static void
+force_vec4(unsigned *classes, unsigned node)
+{
+ if ((node < 0) || (node >= SSA_FIXED_MINIMUM))
+ return;
+
+ /* Force vec4 = 3 */
+ classes[node] |= 0x3;
+}
+
/* Special register classes impose special constraints on who can read their
* values, so check that */
switch (current_class) {
case REG_CLASS_LDST:
+ case REG_CLASS_LDST27:
return (tag == TAG_LOAD_STORE_4);
- default:
+ case REG_CLASS_TEXR:
+ return (tag == TAG_TEXTURE_4);
+ case REG_CLASS_TEXW:
return (tag != TAG_LOAD_STORE_4);
+ case REG_CLASS_WORK:
+ return (tag == TAG_ALU_4);
+ default:
+ unreachable("Invalid class");
+ }
+}
+
+static bool
+check_write_class(unsigned *classes, unsigned tag, unsigned node)
+{
+ /* Non-nodes are implicitly ok */
+ if ((node < 0) || (node >= SSA_FIXED_MINIMUM))
+ return true;
+
+ unsigned current_class = classes[node] >> 2;
+
+ switch (current_class) {
+ case REG_CLASS_TEXR:
+ return true;
+ case REG_CLASS_TEXW:
+ return (tag == TAG_TEXTURE_4);
+ case REG_CLASS_LDST:
+ case REG_CLASS_LDST27:
+ case REG_CLASS_WORK:
+ return (tag == TAG_ALU_4) || (tag == TAG_LOAD_STORE_4);
+ default:
+ unreachable("Invalid class");
+ }
+}
+
+/* Prepass before RA to ensure special class restrictions are met. The idea is
+ * to create a bit field of types of instructions that read a particular index.
+ * Later, we'll add moves as appropriate and rewrite to specialize by type. */
+
+static void
+mark_node_class (unsigned *bitfield, unsigned node)
+{
+ if ((node >= 0) && (node < SSA_FIXED_MINIMUM))
+ BITSET_SET(bitfield, node);
+}
+
+void
+mir_lower_special_reads(compiler_context *ctx)
+{
+ size_t sz = BITSET_WORDS(ctx->temp_count) * sizeof(BITSET_WORD);
+
+ /* Bitfields for the various types of registers we could have */
+
+ unsigned *alur = calloc(sz, 1);
+ unsigned *aluw = calloc(sz, 1);
+ unsigned *ldst = calloc(sz, 1);
+ unsigned *texr = calloc(sz, 1);
+ unsigned *texw = calloc(sz, 1);
+
+ /* Pass #1 is analysis, a linear scan to fill out the bitfields */
+
+ mir_foreach_instr_global(ctx, ins) {
+ if (ins->compact_branch) continue;
+
+ switch (ins->type) {
+ case TAG_ALU_4:
+ mark_node_class(aluw, ins->ssa_args.dest);
+ mark_node_class(alur, ins->ssa_args.src0);
+
+ if (!ins->ssa_args.inline_constant)
+ mark_node_class(alur, ins->ssa_args.src1);
+
+ break;
+ case TAG_LOAD_STORE_4:
+ mark_node_class(ldst, ins->ssa_args.src0);
+ mark_node_class(ldst, ins->ssa_args.src1);
+ break;
+ case TAG_TEXTURE_4:
+ mark_node_class(texr, ins->ssa_args.src0);
+ mark_node_class(texr, ins->ssa_args.src1);
+ mark_node_class(texw, ins->ssa_args.dest);
+ break;
+ }
+ }
+
+ /* Pass #2 is lowering now that we've analyzed all the classes.
+ * Conceptually, if an index is only marked for a single type of use,
+ * there is nothing to lower. If it is marked for different uses, we
+ * split up based on the number of types of uses. To do so, we divide
+ * into N distinct classes of use (where N>1 by definition), emit N-1
+ * moves from the index to copies of the index, and finally rewrite N-1
+ * of the types of uses to use the corresponding move */
+
+ unsigned spill_idx = ctx->temp_count;
+
+ for (unsigned i = 0; i < ctx->temp_count; ++i) {
+ bool is_alur = BITSET_TEST(alur, i);
+ bool is_aluw = BITSET_TEST(aluw, i);
+ bool is_ldst = BITSET_TEST(ldst, i);
+ bool is_texr = BITSET_TEST(texr, i);
+ bool is_texw = BITSET_TEST(texw, i);
+
+ /* Analyse to check how many distinct uses there are. ALU ops
+ * (alur) can read the results of the texture pipeline (texw)
+ * but not ldst or texr. Load/store ops (ldst) cannot read
+ * anything but load/store inputs. Texture pipeline cannot read
+ * anything but texture inputs. TODO: Simplify. */
+
+ bool collision =
+ (is_alur && (is_ldst || is_texr)) ||
+ (is_ldst && (is_alur || is_texr || is_texw)) ||
+ (is_texr && (is_alur || is_ldst || is_texw)) ||
+ (is_texw && (is_aluw || is_ldst || is_texr));
+
+ if (!collision)
+ continue;
+
+ /* Use the index as-is as the work copy. Emit copies for
+ * special uses */
+
+ unsigned classes[] = { TAG_LOAD_STORE_4, TAG_TEXTURE_4, TAG_TEXTURE_4 };
+ bool collisions[] = { is_ldst, is_texr, is_texw && is_aluw };
+
+ for (unsigned j = 0; j < ARRAY_SIZE(collisions); ++j) {
+ if (!collisions[j]) continue;
+
+ /* When the hazard is from reading, we move and rewrite
+ * sources (typical case). When it's from writing, we
+ * flip the move and rewrite destinations (obscure,
+ * only from control flow -- impossible in SSA) */
+
+ bool hazard_write = (j == 2);
+
+ unsigned idx = spill_idx++;
+
+ midgard_instruction m = hazard_write ?
+ v_mov(idx, blank_alu_src, i) :
+ v_mov(i, blank_alu_src, idx);
+
+ /* Insert move after each write */
+ mir_foreach_instr_global_safe(ctx, pre_use) {
+ if (pre_use->compact_branch) continue;
+ if (pre_use->ssa_args.dest != i)
+ continue;
+
+ /* If the hazard is writing, we need to
+ * specific insert moves for the contentious
+ * class. If the hazard is reading, we insert
+ * moves whenever it is written */
+
+ if (hazard_write && pre_use->type != classes[j])
+ continue;
+
+ midgard_instruction *use = mir_next_op(pre_use);
+ assert(use);
+ mir_insert_instruction_before(use, m);
+ }
+
+ /* Rewrite to use */
+ if (hazard_write)
+ mir_rewrite_index_dst_tag(ctx, i, idx, classes[j]);
+ else
+ mir_rewrite_index_src_tag(ctx, i, idx, classes[j]);
+ }
}
+
+ free(alur);
+ free(aluw);
+ free(ldst);
+ free(texr);
+ free(texw);
}
/* This routine performs the actual register allocation. It should be succeeded
/* Check if this operation imposes any classes */
if (ins->type == TAG_LOAD_STORE_4) {
- set_class(found_class, ins->ssa_args.src0, REG_CLASS_LDST);
- set_class(found_class, ins->ssa_args.src1, REG_CLASS_LDST);
+ bool force_r27 = OP_IS_R27_ONLY(ins->load_store.op);
+ unsigned class = force_r27 ? REG_CLASS_LDST27 : REG_CLASS_LDST;
+
+ set_class(found_class, ins->ssa_args.src0, class);
+ set_class(found_class, ins->ssa_args.src1, class);
+
+ if (force_r27) {
+ force_vec4(found_class, ins->ssa_args.dest);
+ force_vec4(found_class, ins->ssa_args.src0);
+ force_vec4(found_class, ins->ssa_args.src1);
+ }
+ } else if (ins->type == TAG_TEXTURE_4) {
+ set_class(found_class, ins->ssa_args.dest, REG_CLASS_TEXW);
+ set_class(found_class, ins->ssa_args.src0, REG_CLASS_TEXR);
+ set_class(found_class, ins->ssa_args.src1, REG_CLASS_TEXR);
}
}
mir_foreach_instr_global(ctx, ins) {
if (ins->compact_branch) continue;
- /* Non-load-store cannot read load/store */
+ assert(check_write_class(found_class, ins->type, ins->ssa_args.dest));
assert(check_read_class(found_class, ins->type, ins->ssa_args.src0));
- assert(check_read_class(found_class, ins->type, ins->ssa_args.src1));
+
+ if (!ins->ssa_args.inline_constant)
+ assert(check_read_class(found_class, ins->type, ins->ssa_args.src1));
}
for (unsigned i = 0; i < ctx->temp_count; ++i) {
unsigned class = found_class[i];
- if (!class) continue;
ra_set_node_class(g, i, classes[class]);
}
}
case TAG_LOAD_STORE_4: {
- if (OP_IS_STORE_R26(ins->load_store.op)) {
- /* TODO: use ssa_args for st_vary */
- ins->load_store.reg = 0;
+ bool fixed = args.src0 >= SSA_FIXED_MINIMUM;
+
+ if (OP_IS_STORE_R26(ins->load_store.op) && fixed) {
+ ins->load_store.reg = SSA_REG_FROM_FIXED(args.src0);
+ } else if (OP_IS_STORE_VARY(ins->load_store.op)) {
+ struct phys_reg src = index_to_reg(ctx, g, args.src0);
+ assert(src.reg == 26 || src.reg == 27);
+
+ ins->load_store.reg = src.reg - 26;
+
+ /* TODO: swizzle/mask */
} else {
/* Which physical register we read off depends on
* whether we are loading or storing -- think about the
* logical dataflow */
- unsigned r = OP_IS_STORE(ins->load_store.op) ?
+ bool encodes_src =
+ OP_IS_STORE(ins->load_store.op) &&
+ ins->load_store.op != midgard_op_st_cubemap_coords;
+
+ unsigned r = encodes_src ?
args.src0 : args.dest;
+
struct phys_reg src = index_to_reg(ctx, g, r);
ins->load_store.reg = src.reg;
break;
}
+ case TAG_TEXTURE_4: {
+ /* Grab RA results */
+ struct phys_reg dest = index_to_reg(ctx, g, args.dest);
+ struct phys_reg coord = index_to_reg(ctx, g, args.src0);
+ struct phys_reg lod = index_to_reg(ctx, g, args.src1);
+
+ assert(dest.reg == 28 || dest.reg == 29);
+ assert(coord.reg == 28 || coord.reg == 29);
+
+ /* First, install the texture coordinate */
+ ins->texture.in_reg_full = 1;
+ ins->texture.in_reg_upper = 0;
+ ins->texture.in_reg_select = coord.reg - 28;
+ ins->texture.in_reg_swizzle =
+ compose_swizzle(ins->texture.in_reg_swizzle, 0xF, coord, dest);
+
+ /* Next, install the destination */
+ ins->texture.out_full = 1;
+ ins->texture.out_upper = 0;
+ ins->texture.out_reg_select = dest.reg - 28;
+ ins->texture.swizzle =
+ compose_swizzle(ins->texture.swizzle, dest.mask, dest, dest);
+ ins->mask =
+ compose_writemask(ins->mask, dest);
+
+ /* If there is a register LOD/bias, use it */
+ if (args.src1 > -1) {
+ midgard_tex_register_select sel = {
+ .select = lod.reg,
+ .full = 1,
+ .component = lod.swizzle & 3,
+ };
+
+ uint8_t packed;
+ memcpy(&packed, &sel, sizeof(packed));
+ ins->texture.bias = packed;
+ }
+
+ break;
+ }
+
default:
break;
}
projects / mesa.git / blobdiff