#include "compiler.h"
#include "midgard_ops.h"
-#include "util/register_allocate.h"
#include "util/u_math.h"
#include "util/u_memory.h"
-
-/* For work registers, we can subdivide in various ways. So we create
- * classes for the various sizes and conflict accordingly, keeping in
- * mind that physical registers are divided along 128-bit boundaries.
- * The important part is that 128-bit boundaries are not crossed.
- *
- * For each 128-bit register, we can subdivide to 32-bits 10 ways
- *
- * vec4: xyzw
- * vec3: xyz, yzw
- * vec2: xy, yz, zw,
- * vec1: x, y, z, w
- *
- * For each 64-bit register, we can subdivide similarly to 16-bit
- * (TODO: half-float RA, not that we support fp16 yet)
- */
-
-#define WORK_STRIDE 10
-
-/* We have overlapping register classes for special registers, handled via
- * shadows */
-
-#define SHADOW_R0 17
-#define SHADOW_R28 18
-#define SHADOW_R29 19
-
-/* Prepacked masks/swizzles for virtual register types */
-static unsigned reg_type_to_mask[WORK_STRIDE] = {
- 0xF, /* xyzw */
- 0x7, 0x7 << 1, /* xyz */
- 0x3, 0x3 << 1, 0x3 << 2, /* xy */
- 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
-};
+#include "lcra.h"
struct phys_reg {
/* Physical register: 0-31 */
unsigned size;
};
-/* Shift each component up by reg_offset and shift all components horizontally
- * by dst_offset. TODO: vec8+ */
+/* Shift up by reg_offset and horizontally by dst_offset. */
static void
-offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset, unsigned dstsize)
+offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset)
{
unsigned out[MIR_VEC_COMPONENTS];
signed reg_comp = reg_offset / srcsize;
- signed dst_comp = dst_offset / dstsize;
+ signed dst_comp = dst_offset / srcsize;
+
+ unsigned max_component = (16 / srcsize) - 1;
assert(reg_comp * srcsize == reg_offset);
- assert(dst_comp * dstsize == dst_offset);
+ assert(dst_comp * srcsize == dst_offset);
for (signed c = 0; c < MIR_VEC_COMPONENTS; ++c) {
signed comp = MAX2(c - dst_comp, 0);
- out[c] = MIN2(swizzle[comp] + reg_comp, 4 - 1);
+ out[c] = MIN2(swizzle[comp] + reg_comp, max_component);
}
memcpy(swizzle, out, sizeof(out));
/* Helper to return the default phys_reg for a given register */
static struct phys_reg
-default_phys_reg(int reg)
+default_phys_reg(int reg, midgard_reg_mode size)
{
struct phys_reg r = {
.reg = reg,
.offset = 0,
- .size = 4
+ .size = mir_bytes_for_mode(size)
};
return r;
* register corresponds to */
static struct phys_reg
-index_to_reg(compiler_context *ctx, struct ra_graph *g, unsigned reg, midgard_reg_mode size)
+index_to_reg(compiler_context *ctx, struct lcra_state *l, unsigned reg, midgard_reg_mode size)
{
/* Check for special cases */
if (reg == ~0)
- return default_phys_reg(REGISTER_UNUSED);
+ return default_phys_reg(REGISTER_UNUSED, size);
else if (reg >= SSA_FIXED_MINIMUM)
- return default_phys_reg(SSA_REG_FROM_FIXED(reg));
- else if (!g)
- return default_phys_reg(REGISTER_UNUSED);
-
- /* Special cases aside, we pick the underlying register */
- int virt = ra_get_node_reg(g, reg);
-
- /* Divide out the register and classification */
- int phys = virt / WORK_STRIDE;
- int type = virt % WORK_STRIDE;
-
- /* Apply shadow registers */
-
- if (phys >= SHADOW_R28 && phys <= SHADOW_R29)
- phys += 28 - SHADOW_R28;
- else if (phys == SHADOW_R0)
- phys = 0;
-
- unsigned bytes = mir_bytes_for_mode(size);
+ return default_phys_reg(SSA_REG_FROM_FIXED(reg), size);
+ else if (!l)
+ return default_phys_reg(REGISTER_UNUSED, size);
struct phys_reg r = {
- .reg = phys,
- .offset = __builtin_ctz(reg_type_to_mask[type]) * bytes,
- .size = bytes
+ .reg = l->solutions[reg] / 16,
+ .offset = l->solutions[reg] & 0xF,
+ .size = mir_bytes_for_mode(size)
};
/* Report that we actually use this register, and return it */
- if (phys < 16)
- ctx->work_registers = MAX2(ctx->work_registers, phys);
+ if (r.reg < 16)
+ ctx->work_registers = MAX2(ctx->work_registers, r.reg);
return r;
}
-/* This routine creates a register set. Should be called infrequently since
- * it's slow and can be cached. For legibility, variables are named in terms of
- * work registers, although it is also used to create the register set for
- * special register allocation */
-
-static void
-add_shadow_conflicts (struct ra_regs *regs, unsigned base, unsigned shadow, unsigned shadow_count)
-{
- for (unsigned a = 0; a < WORK_STRIDE; ++a) {
- unsigned reg_a = (WORK_STRIDE * base) + a;
-
- for (unsigned b = 0; b < shadow_count; ++b) {
- unsigned reg_b = (WORK_STRIDE * shadow) + b;
-
- ra_add_reg_conflict(regs, reg_a, reg_b);
- ra_add_reg_conflict(regs, reg_b, reg_a);
- }
- }
-}
-
-static struct ra_regs *
-create_register_set(unsigned work_count, unsigned *classes)
-{
- int virtual_count = 32 * WORK_STRIDE;
-
- /* First, initialize the RA */
- struct ra_regs *regs = ra_alloc_reg_set(NULL, virtual_count, true);
-
- for (unsigned c = 0; c < (NR_REG_CLASSES - 1); ++c) {
- int work_vec4 = ra_alloc_reg_class(regs);
- int work_vec3 = ra_alloc_reg_class(regs);
- int work_vec2 = ra_alloc_reg_class(regs);
- int work_vec1 = ra_alloc_reg_class(regs);
-
- classes[4*c + 0] = work_vec1;
- classes[4*c + 1] = work_vec2;
- classes[4*c + 2] = work_vec3;
- classes[4*c + 3] = work_vec4;
-
- /* Special register classes have other register counts */
- unsigned count =
- (c == REG_CLASS_WORK) ? work_count : 2;
-
- unsigned first_reg =
- (c == REG_CLASS_LDST) ? 26 :
- (c == REG_CLASS_TEXR) ? 28 :
- (c == REG_CLASS_TEXW) ? SHADOW_R28 :
- 0;
-
- /* Add the full set of work registers */
- for (unsigned i = first_reg; i < (first_reg + count); ++i) {
- int base = WORK_STRIDE * i;
-
- /* Build a full set of subdivisions */
- ra_class_add_reg(regs, work_vec4, base);
- ra_class_add_reg(regs, work_vec3, base + 1);
- ra_class_add_reg(regs, work_vec3, base + 2);
- ra_class_add_reg(regs, work_vec2, base + 3);
- ra_class_add_reg(regs, work_vec2, base + 4);
- ra_class_add_reg(regs, work_vec2, base + 5);
- ra_class_add_reg(regs, work_vec1, base + 6);
- ra_class_add_reg(regs, work_vec1, base + 7);
- ra_class_add_reg(regs, work_vec1, base + 8);
- ra_class_add_reg(regs, work_vec1, base + 9);
-
- for (unsigned a = 0; a < 10; ++a) {
- unsigned mask1 = reg_type_to_mask[a];
-
- for (unsigned b = 0; b < 10; ++b) {
- unsigned mask2 = reg_type_to_mask[b];
-
- if (mask1 & mask2)
- ra_add_reg_conflict(regs,
- base + a, base + b);
- }
- }
- }
- }
-
- int fragc = ra_alloc_reg_class(regs);
-
- classes[4*REG_CLASS_FRAGC + 0] = fragc;
- classes[4*REG_CLASS_FRAGC + 1] = fragc;
- classes[4*REG_CLASS_FRAGC + 2] = fragc;
- classes[4*REG_CLASS_FRAGC + 3] = fragc;
- ra_class_add_reg(regs, fragc, WORK_STRIDE * SHADOW_R0);
-
- /* We have duplicate classes */
- add_shadow_conflicts(regs, 0, SHADOW_R0, 1);
- add_shadow_conflicts(regs, 28, SHADOW_R28, WORK_STRIDE);
- add_shadow_conflicts(regs, 29, SHADOW_R29, WORK_STRIDE);
-
- /* We're done setting up */
- ra_set_finalize(regs, NULL);
-
- return regs;
-}
-
-/* This routine gets a precomputed register set off the screen if it's able, or
- * otherwise it computes one on the fly */
-
-static struct ra_regs *
-get_register_set(struct midgard_screen *screen, unsigned work_count, unsigned **classes)
-{
- /* Bounds check */
- assert(work_count >= 8);
- assert(work_count <= 16);
-
- /* Compute index */
- unsigned index = work_count - 8;
-
- /* Find the reg set */
- struct ra_regs *cached = screen->regs[index];
-
- if (cached) {
- assert(screen->reg_classes[index]);
- *classes = screen->reg_classes[index];
- return cached;
- }
-
- /* Otherwise, create one */
- struct ra_regs *created = create_register_set(work_count, screen->reg_classes[index]);
-
- /* Cache it and use it */
- screen->regs[index] = created;
-
- *classes = screen->reg_classes[index];
- return created;
-}
-
-/* Assign a (special) class, ensuring that it is compatible with whatever class
- * was already set */
-
static void
set_class(unsigned *classes, unsigned node, unsigned class)
{
- /* Check that we're even a node */
- if (node >= SSA_FIXED_MINIMUM)
- return;
-
- /* First 4 are work, next 4 are load/store.. */
- unsigned current_class = classes[node] >> 2;
-
- /* Nothing to do */
- if (class == current_class)
- return;
-
- /* If we're changing, we haven't assigned a special class */
- assert(current_class == REG_CLASS_WORK);
-
- classes[node] &= 0x3;
- classes[node] |= (class << 2);
-}
-
-static void
-force_vec4(unsigned *classes, unsigned node)
-{
- if (node >= SSA_FIXED_MINIMUM)
- return;
-
- /* Force vec4 = 3 */
- classes[node] |= 0x3;
+ if (node < SSA_FIXED_MINIMUM && class != classes[node]) {
+ assert(classes[node] == REG_CLASS_WORK);
+ classes[node] = class;
+ }
}
/* Special register classes impose special constraints on who can read their
if (node >= SSA_FIXED_MINIMUM)
return true;
- unsigned current_class = classes[node] >> 2;
-
- switch (current_class) {
+ switch (classes[node]) {
case REG_CLASS_LDST:
return (tag == TAG_LOAD_STORE_4);
case REG_CLASS_TEXR:
if (node >= SSA_FIXED_MINIMUM)
return true;
- unsigned current_class = classes[node] >> 2;
-
- switch (current_class) {
+ switch (classes[node]) {
case REG_CLASS_TEXR:
return true;
case REG_CLASS_TEXW:
static void
mir_compute_segment_interference(
compiler_context *ctx,
- struct ra_graph *l,
+ struct lcra_state *l,
midgard_bundle *bun,
unsigned pivot,
unsigned i)
continue;
}
- ra_add_node_interference(l, bun->instructions[q]->dest, bun->instructions[j]->src[s]);
+ unsigned mask = mir_bytemask(bun->instructions[q]);
+ unsigned rmask = mir_bytemask_of_read_components(bun->instructions[j], bun->instructions[j]->src[s]);
+ lcra_add_node_interference(l, bun->instructions[q]->dest, mask, bun->instructions[j]->src[s], rmask);
}
}
}
static void
mir_compute_bundle_interference(
compiler_context *ctx,
- struct ra_graph *l,
+ struct lcra_state *l,
midgard_bundle *bun)
{
if (!IS_ALU(bun->tag))
static void
mir_compute_interference(
compiler_context *ctx,
- struct ra_graph *g)
+ struct lcra_state *l)
{
/* First, we need liveness information to be computed per block */
mir_compute_liveness(ctx);
if (dest < ctx->temp_count) {
for (unsigned i = 0; i < ctx->temp_count; ++i)
- if (live[i])
- ra_add_node_interference(g, dest, i);
+ if (live[i]) {
+ unsigned mask = mir_bytemask(ins);
+ lcra_add_node_interference(l, dest, mask, i, live[i]);
+ }
}
/* Update live_in */
}
mir_foreach_bundle_in_block(blk, bun)
- mir_compute_bundle_interference(ctx, g, bun);
+ mir_compute_bundle_interference(ctx, l, bun);
free(live);
}
/* This routine performs the actual register allocation. It should be succeeded
* by install_registers */
-struct ra_graph *
+struct lcra_state *
allocate_registers(compiler_context *ctx, bool *spilled)
{
/* The number of vec4 work registers available depends on when the
* uniforms start, so compute that first */
int work_count = 16 - MAX2((ctx->uniform_cutoff - 8), 0);
- unsigned *classes = NULL;
- struct ra_regs *regs = get_register_set(ctx->screen, work_count, &classes);
-
- assert(regs != NULL);
- assert(classes != NULL);
/* No register allocation to do with no SSA */
if (!ctx->temp_count)
return NULL;
- /* Let's actually do register allocation */
- int nodes = ctx->temp_count;
- struct ra_graph *g = ra_alloc_interference_graph(regs, nodes);
-
- /* Register class (as known to the Mesa register allocator) is actually
- * the product of both semantic class (work, load/store, texture..) and
- * size (vec2/vec3..). First, we'll go through and determine the
- * minimum size needed to hold values */
+ struct lcra_state *l = lcra_alloc_equations(ctx->temp_count, 1, 8, 16, 5);
+
+ /* Starts of classes, in bytes */
+ l->class_start[REG_CLASS_WORK] = 16 * 0;
+ l->class_start[REG_CLASS_LDST] = 16 * 26;
+ l->class_start[REG_CLASS_TEXR] = 16 * 28;
+ l->class_start[REG_CLASS_TEXW] = 16 * 28;
+
+ l->class_size[REG_CLASS_WORK] = 16 * work_count;
+ l->class_size[REG_CLASS_LDST] = 16 * 2;
+ l->class_size[REG_CLASS_TEXR] = 16 * 2;
+ l->class_size[REG_CLASS_TEXW] = 16 * 2;
+
+ lcra_set_disjoint_class(l, REG_CLASS_TEXR, REG_CLASS_TEXW);
unsigned *found_class = calloc(sizeof(unsigned), ctx->temp_count);
int dest = ins->dest;
found_class[dest] = MAX2(found_class[dest], class);
+
+ lcra_set_alignment(l, dest, 2); /* (1 << 2) = 4 */
+
+ /* XXX: Ensure swizzles align the right way with more LCRA constraints? */
+ if (ins->type == TAG_ALU_4 && ins->alu.reg_mode != midgard_reg_mode_32)
+ lcra_set_alignment(l, dest, 3); /* (1 << 3) = 8 */
}
+ for (unsigned i = 0; i < ctx->temp_count; ++i)
+ lcra_restrict_range(l, i, (found_class[i] + 1) * 4);
+
+ free(found_class);
+
/* Next, we'll determine semantic class. We default to zero (work).
* But, if we're used with a special operation, that will force us to a
* particular class. Each node must be assigned to exactly one class; a
/* Check if this operation imposes any classes */
if (ins->type == TAG_LOAD_STORE_4) {
- bool force_vec4_only = OP_IS_VEC4_ONLY(ins->load_store.op);
-
- set_class(found_class, ins->src[0], REG_CLASS_LDST);
- set_class(found_class, ins->src[1], REG_CLASS_LDST);
- set_class(found_class, ins->src[2], REG_CLASS_LDST);
+ set_class(l->class, ins->src[0], REG_CLASS_LDST);
+ set_class(l->class, ins->src[1], REG_CLASS_LDST);
+ set_class(l->class, ins->src[2], REG_CLASS_LDST);
- if (force_vec4_only) {
- force_vec4(found_class, ins->dest);
- force_vec4(found_class, ins->src[0]);
- force_vec4(found_class, ins->src[1]);
- force_vec4(found_class, ins->src[2]);
- }
+ if (OP_IS_VEC4_ONLY(ins->load_store.op))
+ lcra_restrict_range(l, ins->dest, 16);
} else if (ins->type == TAG_TEXTURE_4) {
- set_class(found_class, ins->dest, REG_CLASS_TEXW);
- set_class(found_class, ins->src[0], REG_CLASS_TEXR);
- set_class(found_class, ins->src[1], REG_CLASS_TEXR);
- set_class(found_class, ins->src[2], REG_CLASS_TEXR);
+ set_class(l->class, ins->dest, REG_CLASS_TEXW);
+ set_class(l->class, ins->src[0], REG_CLASS_TEXR);
+ set_class(l->class, ins->src[1], REG_CLASS_TEXR);
+ set_class(l->class, ins->src[2], REG_CLASS_TEXR);
}
}
/* Check that the semantics of the class are respected */
mir_foreach_instr_global(ctx, ins) {
- assert(check_write_class(found_class, ins->type, ins->dest));
- assert(check_read_class(found_class, ins->type, ins->src[0]));
- assert(check_read_class(found_class, ins->type, ins->src[1]));
- assert(check_read_class(found_class, ins->type, ins->src[2]));
+ assert(check_write_class(l->class, ins->type, ins->dest));
+ assert(check_read_class(l->class, ins->type, ins->src[0]));
+ assert(check_read_class(l->class, ins->type, ins->src[1]));
+ assert(check_read_class(l->class, ins->type, ins->src[2]));
}
/* Mark writeout to r0 */
mir_foreach_instr_global(ctx, ins) {
- if (ins->compact_branch && ins->writeout)
- set_class(found_class, ins->src[0], REG_CLASS_FRAGC);
- }
-
- for (unsigned i = 0; i < ctx->temp_count; ++i) {
- unsigned class = found_class[i];
- ra_set_node_class(g, i, classes[class]);
- }
-
- mir_compute_interference(ctx, g);
-
- if (!ra_allocate(g)) {
- *spilled = true;
- } else {
- *spilled = false;
+ if (ins->compact_branch && ins->writeout && ins->src[0] < ctx->temp_count)
+ l->solutions[ins->src[0]] = 0;
}
+
+ mir_compute_interference(ctx, l);
- /* Whether we were successful or not, report the graph so we can
- * compute spill nodes */
-
- return g;
+ *spilled = !lcra_solve(l);
+ return l;
}
/* Once registers have been decided via register allocation
static void
install_registers_instr(
compiler_context *ctx,
- struct ra_graph *g,
+ struct lcra_state *l,
midgard_instruction *ins)
{
switch (ins->type) {
if (ins->compact_branch)
return;
- struct phys_reg src1 = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
- struct phys_reg src2 = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
- struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
+ struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
+ struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
+ struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
dest.offset;
- offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest_offset, dest.size);
+ offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest_offset);
ins->registers.src1_reg = src1.reg;
} else {
midgard_vector_alu_src mod2 =
vector_alu_from_unsigned(ins->alu.src2);
- offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest_offset, dest.size);
+ offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest_offset);
ins->alu.src2 = vector_alu_srco_unsigned(mod2);
ins->registers.src2_reg = src2.reg;
bool encodes_src = OP_IS_STORE(ins->load_store.op);
if (encodes_src) {
- struct phys_reg src = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
+ struct phys_reg src = index_to_reg(ctx, l, ins->src[0], mir_srcsize(ins, 0));
assert(src.reg == 26 || src.reg == 27);
ins->load_store.reg = src.reg - 26;
- offset_swizzle(ins->swizzle[0], src.offset, src.size, 0, 4);
+ offset_swizzle(ins->swizzle[0], src.offset, src.size, 0);
} else {
- struct phys_reg dst = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
+ struct phys_reg dst = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
ins->load_store.reg = dst.reg;
- offset_swizzle(ins->swizzle[0], 0, 4, dst.offset, dst.size);
+ offset_swizzle(ins->swizzle[0], 0, 4, dst.offset);
mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
}
unsigned src3 = ins->src[2];
if (src2 != ~0) {
- struct phys_reg src = index_to_reg(ctx, g, src2, mir_srcsize(ins, 1));
+ struct phys_reg src = index_to_reg(ctx, l, src2, mir_srcsize(ins, 1));
unsigned component = src.offset / src.size;
assert(component * src.size == src.offset);
ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
}
if (src3 != ~0) {
- struct phys_reg src = index_to_reg(ctx, g, src3, mir_srcsize(ins, 2));
+ struct phys_reg src = index_to_reg(ctx, l, src3, mir_srcsize(ins, 2));
unsigned component = src.offset / src.size;
assert(component * src.size == src.offset);
ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
case TAG_TEXTURE_4: {
/* Grab RA results */
- struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
- struct phys_reg coord = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
- struct phys_reg lod = index_to_reg(ctx, g, ins->src[2], mir_srcsize(ins, 2));
-
- assert(dest.reg == 28 || dest.reg == 29);
- assert(coord.reg == 28 || coord.reg == 29);
+ struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins));
+ struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1));
+ struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], mir_srcsize(ins, 2));
/* First, install the texture coordinate */
ins->texture.in_reg_full = 1;
ins->texture.in_reg_upper = 0;
- ins->texture.in_reg_select = coord.reg - 28;
- offset_swizzle(ins->swizzle[1], coord.offset, coord.size, 0, 4);
+ ins->texture.in_reg_select = coord.reg & 1;
+ offset_swizzle(ins->swizzle[1], coord.offset, coord.size, 0);
/* Next, install the destination */
ins->texture.out_full = 1;
ins->texture.out_upper = 0;
- ins->texture.out_reg_select = dest.reg - 28;
- offset_swizzle(ins->swizzle[0], 0, 4, dest.offset, dest.size);
+ ins->texture.out_reg_select = dest.reg & 1;
+ offset_swizzle(ins->swizzle[0], 0, 4, dest.offset);
mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
/* If there is a register LOD/bias, use it */
}
void
-install_registers(compiler_context *ctx, struct ra_graph *g)
+install_registers(compiler_context *ctx, struct lcra_state *l)
{
mir_foreach_instr_global(ctx, ins)
- install_registers_instr(ctx, g, ins);
+ install_registers_instr(ctx, l, ins);
}
projects / mesa.git / blobdiff