/* We have overlapping register classes for special registers, handled via
* shadows */
+#define SHADOW_R0 17
#define SHADOW_R28 18
#define SHADOW_R29 19
0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
};
-static unsigned reg_type_to_swizzle[WORK_STRIDE] = {
- SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
-
- SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
- SWIZZLE(COMPONENT_Y, COMPONENT_Z, COMPONENT_W, COMPONENT_W),
-
- SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
- SWIZZLE(COMPONENT_Y, COMPONENT_Z, COMPONENT_Z, COMPONENT_W),
- SWIZZLE(COMPONENT_Z, COMPONENT_W, COMPONENT_Z, COMPONENT_W),
-
- SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
- SWIZZLE(COMPONENT_Y, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
- SWIZZLE(COMPONENT_Z, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
- SWIZZLE(COMPONENT_W, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
-};
-
struct phys_reg {
+ /* Physical register: 0-31 */
unsigned reg;
- unsigned mask;
- unsigned swizzle;
-};
-/* Given the mask/swizzle of both the register and the original source,
- * compose to find the actual mask/swizzle to give the hardware */
+ /* Byte offset into the physical register: 0-15 */
+ unsigned offset;
-static unsigned
-compose_writemask(unsigned mask, struct phys_reg reg)
-{
- /* Note: the reg mask is guaranteed to be contiguous. So we shift
- * into the X place, compose via a simple AND, and shift back */
+ /* Number of bytes in a component of this register */
+ unsigned size;
+};
- unsigned shift = __builtin_ctz(reg.mask);
- return ((reg.mask >> shift) & mask) << shift;
-}
+/* Shift each component up by reg_offset and shift all components horizontally
+ * by dst_offset. TODO: vec8+ */
-static unsigned
-compose_swizzle(unsigned swizzle, unsigned mask,
- struct phys_reg reg, struct phys_reg dst)
+static void
+offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset, unsigned dstsize)
{
- unsigned out = pan_compose_swizzle(swizzle, reg.swizzle);
-
- /* Based on the register mask, we need to adjust over. E.g if we're
- * writing to yz, a base swizzle of xy__ becomes _xy_. Save the
- * original first component (x). But to prevent duplicate shifting
- * (only applies to ALU -- mask param is set to xyzw out on L/S to
- * prevent changes), we have to account for the shift inherent to the
- * original writemask */
+ unsigned out[MIR_VEC_COMPONENTS];
- unsigned rep = out & 0x3;
- unsigned shift = __builtin_ctz(dst.mask) - __builtin_ctz(mask);
- unsigned shifted = out << (2*shift);
+ signed reg_comp = reg_offset / srcsize;
+ signed dst_comp = dst_offset / dstsize;
- /* ..but we fill in the gaps so it appears to replicate */
+ assert(reg_comp * srcsize == reg_offset);
+ assert(dst_comp * dstsize == dst_offset);
- for (unsigned s = 0; s < shift; ++s)
- shifted |= rep << (2*s);
+ for (signed c = 0; c < MIR_VEC_COMPONENTS; ++c) {
+ signed comp = MAX2(c - dst_comp, 0);
+ out[c] = MIN2(swizzle[comp] + reg_comp, 4 - 1);
+ }
- return shifted;
+ memcpy(swizzle, out, sizeof(out));
}
/* Helper to return the default phys_reg for a given register */
{
struct phys_reg r = {
.reg = reg,
- .mask = 0xF, /* xyzw */
- .swizzle = 0xE4 /* xyzw */
+ .offset = 0,
+ .size = 4
};
return r;
* register corresponds to */
static struct phys_reg
-index_to_reg(compiler_context *ctx, struct ra_graph *g, unsigned reg)
+index_to_reg(compiler_context *ctx, struct ra_graph *g, unsigned reg, midgard_reg_mode size)
{
/* Check for special cases */
- if ((reg == ~0) && g)
+ if (reg == ~0)
return default_phys_reg(REGISTER_UNUSED);
else if (reg >= SSA_FIXED_MINIMUM)
return default_phys_reg(SSA_REG_FROM_FIXED(reg));
if (phys >= SHADOW_R28 && phys <= SHADOW_R29)
phys += 28 - SHADOW_R28;
+ else if (phys == SHADOW_R0)
+ phys = 0;
+
+ unsigned bytes = mir_bytes_for_mode(size);
struct phys_reg r = {
.reg = phys,
- .mask = reg_type_to_mask[type],
- .swizzle = reg_type_to_swizzle[type]
+ .offset = __builtin_ctz(reg_type_to_mask[type]) * bytes,
+ .size = bytes
};
/* Report that we actually use this register, and return it */
* special register allocation */
static void
-add_shadow_conflicts (struct ra_regs *regs, unsigned base, unsigned shadow)
+add_shadow_conflicts (struct ra_regs *regs, unsigned base, unsigned shadow, unsigned shadow_count)
{
for (unsigned a = 0; a < WORK_STRIDE; ++a) {
unsigned reg_a = (WORK_STRIDE * base) + a;
- for (unsigned b = 0; b < WORK_STRIDE; ++b) {
+ for (unsigned b = 0; b < shadow_count; ++b) {
unsigned reg_b = (WORK_STRIDE * shadow) + b;
ra_add_reg_conflict(regs, reg_a, reg_b);
/* First, initialize the RA */
struct ra_regs *regs = ra_alloc_reg_set(NULL, virtual_count, true);
- for (unsigned c = 0; c < NR_REG_CLASSES; ++c) {
+ for (unsigned c = 0; c < (NR_REG_CLASSES - 1); ++c) {
int work_vec4 = ra_alloc_reg_class(regs);
int work_vec3 = ra_alloc_reg_class(regs);
int work_vec2 = ra_alloc_reg_class(regs);
}
}
+ int fragc = ra_alloc_reg_class(regs);
+
+ classes[4*REG_CLASS_FRAGC + 0] = fragc;
+ classes[4*REG_CLASS_FRAGC + 1] = fragc;
+ classes[4*REG_CLASS_FRAGC + 2] = fragc;
+ classes[4*REG_CLASS_FRAGC + 3] = fragc;
+ ra_class_add_reg(regs, fragc, WORK_STRIDE * SHADOW_R0);
/* We have duplicate classes */
- add_shadow_conflicts(regs, 28, SHADOW_R28);
- add_shadow_conflicts(regs, 29, SHADOW_R29);
+ add_shadow_conflicts(regs, 0, SHADOW_R0, 1);
+ add_shadow_conflicts(regs, 28, SHADOW_R28, WORK_STRIDE);
+ add_shadow_conflicts(regs, 29, SHADOW_R29, WORK_STRIDE);
/* We're done setting up */
ra_set_finalize(regs, NULL);
case REG_CLASS_TEXW:
return (tag != TAG_LOAD_STORE_4);
case REG_CLASS_WORK:
- return (tag == TAG_ALU_4);
+ return IS_ALU(tag);
default:
unreachable("Invalid class");
}
return (tag == TAG_TEXTURE_4);
case REG_CLASS_LDST:
case REG_CLASS_WORK:
- return (tag == TAG_ALU_4) || (tag == TAG_LOAD_STORE_4);
+ return IS_ALU(tag) || (tag == TAG_LOAD_STORE_4);
default:
unreachable("Invalid class");
}
{
size_t sz = BITSET_WORDS(ctx->temp_count) * sizeof(BITSET_WORD);
- /* Bitfields for the various types of registers we could have */
+ /* Bitfields for the various types of registers we could have. aluw can
+ * be written by either ALU or load/store */
unsigned *alur = calloc(sz, 1);
unsigned *aluw = calloc(sz, 1);
+ unsigned *brar = calloc(sz, 1);
unsigned *ldst = calloc(sz, 1);
unsigned *texr = calloc(sz, 1);
unsigned *texw = calloc(sz, 1);
mark_node_class(aluw, ins->dest);
mark_node_class(alur, ins->src[0]);
mark_node_class(alur, ins->src[1]);
+ mark_node_class(alur, ins->src[2]);
+
+ if (ins->compact_branch && ins->writeout)
+ mark_node_class(brar, ins->src[0]);
+
break;
case TAG_LOAD_STORE_4:
+ mark_node_class(aluw, ins->dest);
mark_node_class(ldst, ins->src[0]);
mark_node_class(ldst, ins->src[1]);
mark_node_class(ldst, ins->src[2]);
for (unsigned i = 0; i < ctx->temp_count; ++i) {
bool is_alur = BITSET_TEST(alur, i);
bool is_aluw = BITSET_TEST(aluw, i);
+ bool is_brar = BITSET_TEST(brar, i);
bool is_ldst = BITSET_TEST(ldst, i);
bool is_texr = BITSET_TEST(texr, i);
bool is_texw = BITSET_TEST(texw, i);
(is_alur && (is_ldst || is_texr)) ||
(is_ldst && (is_alur || is_texr || is_texw)) ||
(is_texr && (is_alur || is_ldst || is_texw)) ||
- (is_texw && (is_aluw || is_ldst || is_texr));
+ (is_texw && (is_aluw || is_ldst || is_texr)) ||
+ (is_brar && is_texw);
if (!collision)
continue;
/* Use the index as-is as the work copy. Emit copies for
* special uses */
- unsigned classes[] = { TAG_LOAD_STORE_4, TAG_TEXTURE_4, TAG_TEXTURE_4 };
- bool collisions[] = { is_ldst, is_texr, is_texw && is_aluw };
+ unsigned classes[] = { TAG_LOAD_STORE_4, TAG_TEXTURE_4, TAG_TEXTURE_4, TAG_ALU_4};
+ bool collisions[] = { is_ldst, is_texr, is_texw && is_aluw, is_brar };
for (unsigned j = 0; j < ARRAY_SIZE(collisions); ++j) {
if (!collisions[j]) continue;
unsigned idx = spill_idx++;
midgard_instruction m = hazard_write ?
- v_mov(idx, blank_alu_src, i) :
- v_mov(i, blank_alu_src, idx);
+ v_mov(idx, i) : v_mov(i, idx);
/* Insert move before each read/write, depending on the
* hazard we're trying to account for */
if (hazard_write) {
midgard_instruction *use = mir_next_op(pre_use);
assert(use);
- mir_insert_instruction_before(use, m);
+ mir_insert_instruction_before(ctx, use, m);
mir_rewrite_index_dst_single(pre_use, i, idx);
} else {
idx = spill_idx++;
- m = v_mov(i, blank_alu_src, idx);
- m.mask = mir_mask_of_read_components(pre_use, i);
- mir_insert_instruction_before(pre_use, m);
+ m = v_mov(i, idx);
+ m.mask = mir_from_bytemask(mir_bytemask_of_read_components(pre_use, i), midgard_reg_mode_32);
+ mir_insert_instruction_before(ctx, pre_use, m);
mir_rewrite_index_src_single(pre_use, i, idx);
}
}
free(alur);
free(aluw);
+ free(brar);
free(ldst);
free(texr);
free(texw);
}
-/* Routines for liveness analysis */
-
-static void
-liveness_gen(uint8_t *live, unsigned node, unsigned max, unsigned mask)
-{
- if (node >= max)
- return;
-
- live[node] |= mask;
-}
-
-static void
-liveness_kill(uint8_t *live, unsigned node, unsigned max, unsigned mask)
-{
- if (node >= max)
- return;
-
- live[node] &= ~mask;
-}
-
-/* Updates live_in for a single instruction */
-
-static void
-liveness_ins_update(uint8_t *live, midgard_instruction *ins, unsigned max)
-{
- /* live_in[s] = GEN[s] + (live_out[s] - KILL[s]) */
-
- liveness_kill(live, ins->dest, max, ins->mask);
-
- mir_foreach_src(ins, src) {
- unsigned node = ins->src[src];
- unsigned mask = mir_mask_of_read_components(ins, node);
-
- liveness_gen(live, node, max, mask);
- }
-}
-
-/* live_out[s] = sum { p in succ[s] } ( live_in[p] ) */
-
-static void
-liveness_block_live_out(compiler_context *ctx, midgard_block *blk)
-{
- mir_foreach_successor(blk, succ) {
- for (unsigned i = 0; i < ctx->temp_count; ++i)
- blk->live_out[i] |= succ->live_in[i];
- }
-}
-
-/* Liveness analysis is a backwards-may dataflow analysis pass. Within a block,
- * we compute live_out from live_in. The intrablock pass is linear-time. It
- * returns whether progress was made. */
-
-static bool
-liveness_block_update(compiler_context *ctx, midgard_block *blk)
-{
- bool progress = false;
-
- liveness_block_live_out(ctx, blk);
-
- uint8_t *live = mem_dup(blk->live_out, ctx->temp_count);
-
- mir_foreach_instr_in_block_rev(blk, ins)
- liveness_ins_update(live, ins, ctx->temp_count);
-
- /* To figure out progress, diff live_in */
-
- for (unsigned i = 0; (i < ctx->temp_count) && !progress; ++i)
- progress |= (blk->live_in[i] != live[i]);
-
- free(blk->live_in);
- blk->live_in = live;
-
- return progress;
-}
-
-/* Globally, liveness analysis uses a fixed-point algorithm based on a
- * worklist. We initialize a work list with the exit block. We iterate the work
- * list to compute live_in from live_out for each block on the work list,
- * adding the predecessors of the block to the work list if we made progress.
- */
-
static void
-mir_compute_liveness(
+mir_compute_interference(
compiler_context *ctx,
struct ra_graph *g)
{
- /* List of midgard_block */
- struct set *work_list;
-
- work_list = _mesa_set_create(ctx,
- _mesa_hash_pointer,
- _mesa_key_pointer_equal);
-
- /* Allocate */
-
- mir_foreach_block(ctx, block) {
- block->live_in = calloc(ctx->temp_count, 1);
- block->live_out = calloc(ctx->temp_count, 1);
- }
-
- /* Initialize the work list with the exit block */
- struct set_entry *cur;
-
- midgard_block *exit = mir_exit_block(ctx);
- cur = _mesa_set_add(work_list, exit);
-
- /* Iterate the work list */
-
- do {
- /* Pop off a block */
- midgard_block *blk = (struct midgard_block *) cur->key;
- _mesa_set_remove(work_list, cur);
-
- /* Update its liveness information */
- bool progress = liveness_block_update(ctx, blk);
-
- /* If we made progress, we need to process the predecessors */
-
- if (progress || (blk == exit)) {
- mir_foreach_predecessor(blk, pred)
- _mesa_set_add(work_list, pred);
- }
- } while((cur = _mesa_set_next_entry(work_list, NULL)) != NULL);
+ /* First, we need liveness information to be computed per block */
+ mir_compute_liveness(ctx);
/* Now that every block has live_in/live_out computed, we can determine
* interference by walking each block linearly. Take live_out at the
* end of each block and walk the block backwards. */
mir_foreach_block(ctx, blk) {
- uint8_t *live = calloc(ctx->temp_count, 1);
-
- mir_foreach_successor(blk, succ) {
- for (unsigned i = 0; i < ctx->temp_count; ++i)
- live[i] |= succ->live_in[i];
- }
+ uint16_t *live = mem_dup(blk->live_out, ctx->temp_count * sizeof(uint16_t));
mir_foreach_instr_in_block_rev(blk, ins) {
/* Mark all registers live after the instruction as
}
/* Update live_in */
- liveness_ins_update(live, ins, ctx->temp_count);
+ mir_liveness_ins_update(live, ins, ctx->temp_count);
}
free(live);
}
-
- mir_foreach_block(ctx, blk) {
- free(blk->live_in);
- free(blk->live_out);
- }
}
/* This routine performs the actual register allocation. It should be succeeded
assert(check_read_class(found_class, ins->type, ins->src[2]));
}
+ /* Mark writeout to r0 */
+ mir_foreach_instr_global(ctx, ins) {
+ if (ins->compact_branch && ins->writeout)
+ set_class(found_class, ins->src[0], REG_CLASS_FRAGC);
+ }
+
for (unsigned i = 0; i < ctx->temp_count; ++i) {
unsigned class = found_class[i];
ra_set_node_class(g, i, classes[class]);
}
- mir_compute_liveness(ctx, g);
+ mir_compute_interference(ctx, g);
if (!ra_allocate(g)) {
*spilled = true;
midgard_instruction *ins)
{
switch (ins->type) {
- case TAG_ALU_4: {
- struct phys_reg src1 = index_to_reg(ctx, g, ins->src[0]);
- struct phys_reg src2 = index_to_reg(ctx, g, ins->src[1]);
- struct phys_reg dest = index_to_reg(ctx, g, ins->dest);
+ case TAG_ALU_4:
+ case TAG_ALU_8:
+ case TAG_ALU_12:
+ case TAG_ALU_16: {
+ if (ins->compact_branch)
+ return;
- unsigned uncomposed_mask = ins->mask;
- ins->mask = compose_writemask(uncomposed_mask, dest);
+ struct phys_reg src1 = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
+ struct phys_reg src2 = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
+ struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
- /* Adjust the dest mask if necessary. Mostly this is a no-op
- * but it matters for dot products */
- dest.mask = effective_writemask(&ins->alu, ins->mask);
+ mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
- midgard_vector_alu_src mod1 =
- vector_alu_from_unsigned(ins->alu.src1);
- mod1.swizzle = compose_swizzle(mod1.swizzle, uncomposed_mask, src1, dest);
- ins->alu.src1 = vector_alu_srco_unsigned(mod1);
+ unsigned dest_offset =
+ GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
+ dest.offset;
+
+ offset_swizzle(ins->swizzle[0], src1.offset, src1.size, dest_offset, dest.size);
ins->registers.src1_reg = src1.reg;
} else {
midgard_vector_alu_src mod2 =
vector_alu_from_unsigned(ins->alu.src2);
- mod2.swizzle = compose_swizzle(
- mod2.swizzle, uncomposed_mask, src2, dest);
+ offset_swizzle(ins->swizzle[1], src2.offset, src2.size, dest_offset, dest.size);
ins->alu.src2 = vector_alu_srco_unsigned(mod2);
ins->registers.src2_reg = src2.reg;
bool encodes_src = OP_IS_STORE(ins->load_store.op);
if (encodes_src) {
- struct phys_reg src = index_to_reg(ctx, g, ins->src[0]);
+ struct phys_reg src = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
assert(src.reg == 26 || src.reg == 27);
ins->load_store.reg = src.reg - 26;
-
- unsigned shift = __builtin_ctz(src.mask);
- unsigned adjusted_mask = src.mask >> shift;
- assert(((adjusted_mask + 1) & adjusted_mask) == 0);
-
- unsigned new_swizzle = 0;
- for (unsigned q = 0; q < 4; ++q) {
- unsigned c = (ins->load_store.swizzle >> (2*q)) & 3;
- new_swizzle |= (c + shift) << (2*q);
- }
-
- ins->load_store.swizzle = compose_swizzle(
- new_swizzle, src.mask,
- default_phys_reg(0), src);
+ offset_swizzle(ins->swizzle[0], src.offset, src.size, 0, 4);
} else {
- struct phys_reg src = index_to_reg(ctx, g, ins->dest);
-
- ins->load_store.reg = src.reg;
+ struct phys_reg dst = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
- ins->load_store.swizzle = compose_swizzle(
- ins->load_store.swizzle, 0xF,
- default_phys_reg(0), src);
-
- ins->mask = compose_writemask(
- ins->mask, src);
+ ins->load_store.reg = dst.reg;
+ offset_swizzle(ins->swizzle[0], 0, 4, dst.offset, dst.size);
+ mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
}
/* We also follow up by actual arguments */
- int src2 =
- encodes_src ? ins->src[1] : ins->src[0];
-
- int src3 =
- encodes_src ? ins->src[2] : ins->src[1];
+ unsigned src2 = ins->src[1];
+ unsigned src3 = ins->src[2];
- if (src2 >= 0) {
- struct phys_reg src = index_to_reg(ctx, g, src2);
- unsigned component = __builtin_ctz(src.mask);
+ if (src2 != ~0) {
+ struct phys_reg src = index_to_reg(ctx, g, src2, mir_srcsize(ins, 1));
+ unsigned component = src.offset / src.size;
+ assert(component * src.size == src.offset);
ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
}
- if (src3 >= 0) {
- struct phys_reg src = index_to_reg(ctx, g, src3);
- unsigned component = __builtin_ctz(src.mask);
+ if (src3 != ~0) {
+ struct phys_reg src = index_to_reg(ctx, g, src3, mir_srcsize(ins, 2));
+ unsigned component = src.offset / src.size;
+ assert(component * src.size == src.offset);
ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
}
case TAG_TEXTURE_4: {
/* Grab RA results */
- struct phys_reg dest = index_to_reg(ctx, g, ins->dest);
- struct phys_reg coord = index_to_reg(ctx, g, ins->src[0]);
- struct phys_reg lod = index_to_reg(ctx, g, ins->src[1]);
+ struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
+ struct phys_reg coord = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
+ struct phys_reg lod = index_to_reg(ctx, g, ins->src[2], mir_srcsize(ins, 2));
assert(dest.reg == 28 || dest.reg == 29);
assert(coord.reg == 28 || coord.reg == 29);
ins->texture.in_reg_full = 1;
ins->texture.in_reg_upper = 0;
ins->texture.in_reg_select = coord.reg - 28;
- ins->texture.in_reg_swizzle =
- compose_swizzle(ins->texture.in_reg_swizzle, 0xF, coord, dest);
+ offset_swizzle(ins->swizzle[1], coord.offset, coord.size, 0, 4);
/* Next, install the destination */
ins->texture.out_full = 1;
ins->texture.out_upper = 0;
ins->texture.out_reg_select = dest.reg - 28;
- ins->texture.swizzle =
- compose_swizzle(ins->texture.swizzle, dest.mask, dest, dest);
- ins->mask =
- compose_writemask(ins->mask, dest);
+ offset_swizzle(ins->swizzle[0], 0, 4, dest.offset, dest.size);
+ mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
/* If there is a register LOD/bias, use it */
- if (ins->src[1] != ~0) {
+ if (ins->src[2] != ~0) {
+ assert(!(lod.offset & 3));
midgard_tex_register_select sel = {
.select = lod.reg,
.full = 1,
- .component = lod.swizzle & 3,
+ .component = lod.offset / 4
};
uint8_t packed;
void
install_registers(compiler_context *ctx, struct ra_graph *g)
{
- mir_foreach_block(ctx, block) {
- mir_foreach_instr_in_block(block, ins) {
- install_registers_instr(ctx, g, ins);
- }
- }
-
+ mir_foreach_instr_global(ctx, ins)
+ install_registers_instr(ctx, g, ins);
}
projects / mesa.git / blobdiff