#include "compiler.h"
#include "midgard_ops.h"
+#include "midgard_quirks.h"
#include "util/u_memory.h"
-#include "util/register_allocate.h"
+#include "util/u_math.h"
-/* Create a mask of accessed components from a swizzle to figure out vector
- * dependencies */
+/* Scheduling for Midgard is complicated, to say the least. ALU instructions
+ * must be grouped into VLIW bundles according to following model:
+ *
+ * [VMUL] [SADD]
+ * [VADD] [SMUL] [VLUT]
+ *
+ * A given instruction can execute on some subset of the units (or a few can
+ * execute on all). Instructions can be either vector or scalar; only scalar
+ * instructions can execute on SADD/SMUL units. Units on a given line execute
+ * in parallel. Subsequent lines execute separately and can pass results
+ * directly via pipeline registers r24/r25, bypassing the register file.
+ *
+ * A bundle can optionally have 128-bits of embedded constants, shared across
+ * all of the instructions within a bundle.
+ *
+ * Instructions consuming conditionals (branches and conditional selects)
+ * require their condition to be written into the conditional register (r31)
+ * within the same bundle they are consumed.
+ *
+ * Fragment writeout requires its argument to be written in full within the
+ * same bundle as the branch, with no hanging dependencies.
+ *
+ * Load/store instructions are also in bundles of simply two instructions, and
+ * texture instructions have no bundling.
+ *
+ * -------------------------------------------------------------------------
+ *
+ */
-static unsigned
-swizzle_to_access_mask(unsigned swizzle)
+/* We create the dependency graph with per-byte granularity */
+
+#define BYTE_COUNT 16
+
+static void
+add_dependency(struct util_dynarray *table, unsigned index, uint16_t mask, midgard_instruction **instructions, unsigned child)
+{
+ for (unsigned i = 0; i < BYTE_COUNT; ++i) {
+ if (!(mask & (1 << i)))
+ continue;
+
+ struct util_dynarray *parents = &table[(BYTE_COUNT * index) + i];
+
+ util_dynarray_foreach(parents, unsigned, parent) {
+ BITSET_WORD *dependents = instructions[*parent]->dependents;
+
+ /* Already have the dependency */
+ if (BITSET_TEST(dependents, child))
+ continue;
+
+ BITSET_SET(dependents, child);
+ instructions[child]->nr_dependencies++;
+ }
+ }
+}
+
+static void
+mark_access(struct util_dynarray *table, unsigned index, uint16_t mask, unsigned parent)
{
- unsigned component_mask = 0;
+ for (unsigned i = 0; i < BYTE_COUNT; ++i) {
+ if (!(mask & (1 << i)))
+ continue;
+
+ util_dynarray_append(&table[(BYTE_COUNT * index) + i], unsigned, parent);
+ }
+}
+
+static void
+mir_create_dependency_graph(midgard_instruction **instructions, unsigned count, unsigned node_count)
+{
+ size_t sz = node_count * BYTE_COUNT;
+
+ struct util_dynarray *last_read = calloc(sizeof(struct util_dynarray), sz);
+ struct util_dynarray *last_write = calloc(sizeof(struct util_dynarray), sz);
+
+ for (unsigned i = 0; i < sz; ++i) {
+ util_dynarray_init(&last_read[i], NULL);
+ util_dynarray_init(&last_write[i], NULL);
+ }
+
+ /* Initialize dependency graph */
+ for (unsigned i = 0; i < count; ++i) {
+ instructions[i]->dependents =
+ calloc(BITSET_WORDS(count), sizeof(BITSET_WORD));
+
+ instructions[i]->nr_dependencies = 0;
+ }
+
+ /* Populate dependency graph */
+ for (signed i = count - 1; i >= 0; --i) {
+ if (instructions[i]->compact_branch)
+ continue;
+
+ unsigned dest = instructions[i]->dest;
+ unsigned mask = mir_bytemask(instructions[i]);
+
+ mir_foreach_src((*instructions), s) {
+ unsigned src = instructions[i]->src[s];
+
+ if (src < node_count) {
+ unsigned readmask = mir_bytemask_of_read_components(instructions[i], src);
+ add_dependency(last_write, src, readmask, instructions, i);
+ }
+ }
+
+ if (dest < node_count) {
+ add_dependency(last_read, dest, mask, instructions, i);
+ add_dependency(last_write, dest, mask, instructions, i);
+ mark_access(last_write, dest, mask, i);
+ }
+
+ mir_foreach_src((*instructions), s) {
+ unsigned src = instructions[i]->src[s];
+
+ if (src < node_count) {
+ unsigned readmask = mir_bytemask_of_read_components(instructions[i], src);
+ mark_access(last_read, src, readmask, i);
+ }
+ }
+ }
+
+ /* If there is a branch, all instructions depend on it, as interblock
+ * execution must be purely in-order */
+
+ if (instructions[count - 1]->compact_branch) {
+ BITSET_WORD *dependents = instructions[count - 1]->dependents;
+
+ for (signed i = count - 2; i >= 0; --i) {
+ if (BITSET_TEST(dependents, i))
+ continue;
- for (int i = 0; i < 4; ++i) {
- unsigned c = (swizzle >> (2 * i)) & 3;
- component_mask |= (1 << c);
+ BITSET_SET(dependents, i);
+ instructions[i]->nr_dependencies++;
+ }
+ }
+
+ /* Free the intermediate structures */
+ for (unsigned i = 0; i < sz; ++i) {
+ util_dynarray_fini(&last_read[i]);
+ util_dynarray_fini(&last_write[i]);
}
- return component_mask;
+ free(last_read);
+ free(last_write);
}
/* Does the mask cover more than a scalar? */
return components == 1;
}
-/* Checks for an SSA data hazard between two adjacent instructions, keeping in
- * mind that we are a vector architecture and we can write to different
- * components simultaneously */
+/* Helpers for scheudling */
static bool
-can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second)
+mir_is_scalar(midgard_instruction *ains)
{
- /* Each instruction reads some registers and writes to a register. See
- * where the first writes */
-
- /* Figure out where exactly we wrote to */
- int source = first->ssa_args.dest;
- int source_mask = first->mask;
-
- /* As long as the second doesn't read from the first, we're okay */
- if (second->ssa_args.src[0] == source) {
- if (first->type == TAG_ALU_4) {
- /* Figure out which components we just read from */
+ /* Do we try to use it as a vector op? */
+ if (!is_single_component_mask(ains->mask))
+ return false;
- int q = second->alu.src1;
- midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
+ /* Otherwise, check mode hazards */
+ bool could_scalar = true;
- /* Check if there are components in common, and fail if so */
- if (swizzle_to_access_mask(m->swizzle) & source_mask)
- return false;
- } else
- return false;
+ /* Only 16/32-bit can run on a scalar unit */
+ could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8;
+ could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64;
+ could_scalar &= ains->alu.dest_override == midgard_dest_override_none;
- }
+ if (ains->alu.reg_mode == midgard_reg_mode_16) {
+ /* If we're running in 16-bit mode, we
+ * can't have any 8-bit sources on the
+ * scalar unit (since the scalar unit
+ * doesn't understand 8-bit) */
- if (second->ssa_args.src[1] == source)
- return false;
+ midgard_vector_alu_src s1 =
+ vector_alu_from_unsigned(ains->alu.src1);
- /* Otherwise, it's safe in that regard. Another data hazard is both
- * writing to the same place, of course */
+ could_scalar &= !s1.half;
- if (second->ssa_args.dest == source) {
- /* ...but only if the components overlap */
+ midgard_vector_alu_src s2 =
+ vector_alu_from_unsigned(ains->alu.src2);
- if (second->mask & source_mask)
- return false;
+ could_scalar &= !s2.half;
}
- /* ...That's it */
- return true;
+ return could_scalar;
}
-static bool
-midgard_has_hazard(
- midgard_instruction **segment, unsigned segment_size,
- midgard_instruction *ains)
-{
- for (int s = 0; s < segment_size; ++s)
- if (!can_run_concurrent_ssa(segment[s], ains))
- return true;
-
- return false;
-
+/* How many bytes does this ALU instruction add to the bundle? */
+static unsigned
+bytes_for_instruction(midgard_instruction *ains)
+{
+ if (ains->unit & UNITS_ANY_VECTOR)
+ return sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
+ else if (ains->unit == ALU_ENAB_BRANCH)
+ return sizeof(midgard_branch_extended);
+ else if (ains->compact_branch)
+ return sizeof(ains->br_compact);
+ else
+ return sizeof(midgard_reg_info) + sizeof(midgard_scalar_alu);
}
-/* Fragment writeout (of r0) is allowed when:
- *
- * - All components of r0 are written in the bundle
- * - No components of r0 are written in VLUT
- * - Non-pipelined dependencies of r0 are not written in the bundle
- *
- * This function checks if these requirements are satisfied given the content
- * of a scheduled bundle.
- */
+/* We would like to flatten the linked list of midgard_instructions in a bundle
+ * to an array of pointers on the heap for easy indexing */
-static bool
-can_writeout_fragment(compiler_context *ctx, midgard_instruction **bundle, unsigned count, unsigned node_count)
+static midgard_instruction **
+flatten_mir(midgard_block *block, unsigned *len)
{
- /* First scan for which components of r0 are written out. Initially
- * none are written */
-
- uint8_t r0_written_mask = 0x0;
+ *len = list_length(&block->base.instructions);
- /* Simultaneously we scan for the set of dependencies */
- BITSET_WORD *dependencies = calloc(sizeof(BITSET_WORD), BITSET_WORDS(node_count));
+ if (!(*len))
+ return NULL;
- for (unsigned i = 0; i < count; ++i) {
- midgard_instruction *ins = bundle[i];
+ midgard_instruction **instructions =
+ calloc(sizeof(midgard_instruction *), *len);
- if (ins->ssa_args.dest != SSA_FIXED_REGISTER(0))
- continue;
+ unsigned i = 0;
- /* Record written out mask */
- r0_written_mask |= ins->mask;
+ mir_foreach_instr_in_block(block, ins)
+ instructions[i++] = ins;
- /* Record dependencies, but only if they won't become pipeline
- * registers. We know we can't be live after this, because
- * we're writeout at the very end of the shader. So check if
- * they were written before us. */
+ return instructions;
+}
- unsigned src0 = ins->ssa_args.src[0];
- unsigned src1 = ins->ssa_args.src[1];
+/* The worklist is the set of instructions that can be scheduled now; that is,
+ * the set of instructions with no remaining dependencies */
- if (!mir_is_written_before(ctx, bundle[0], src0))
- src0 = -1;
+static void
+mir_initialize_worklist(BITSET_WORD *worklist, midgard_instruction **instructions, unsigned count)
+{
+ for (unsigned i = 0; i < count; ++i) {
+ if (instructions[i]->nr_dependencies == 0)
+ BITSET_SET(worklist, i);
+ }
+}
- if (!mir_is_written_before(ctx, bundle[0], src1))
- src1 = -1;
+/* Update the worklist after an instruction terminates. Remove its edges from
+ * the graph and if that causes any node to have no dependencies, add it to the
+ * worklist */
- if ((src0 > 0) && (src0 < node_count))
- BITSET_SET(dependencies, src0);
+static void
+mir_update_worklist(
+ BITSET_WORD *worklist, unsigned count,
+ midgard_instruction **instructions, midgard_instruction *done)
+{
+ /* Sanity check: if no instruction terminated, there is nothing to do.
+ * If the instruction that terminated had dependencies, that makes no
+ * sense and means we messed up the worklist. Finally, as the purpose
+ * of this routine is to update dependents, we abort early if there are
+ * no dependents defined. */
- if ((src1 > 0) && (src1 < node_count))
- BITSET_SET(dependencies, src1);
+ if (!done)
+ return;
- /* Requirement 2 */
- if (ins->unit == UNIT_VLUT)
- return false;
- }
+ assert(done->nr_dependencies == 0);
- /* Requirement 1 */
- if ((r0_written_mask & 0xF) != 0xF)
- return false;
+ if (!done->dependents)
+ return;
- /* Requirement 3 */
+ /* We have an instruction with dependents. Iterate each dependent to
+ * remove one dependency (`done`), adding dependents to the worklist
+ * where possible. */
- for (unsigned i = 0; i < count; ++i) {
- unsigned dest = bundle[i]->ssa_args.dest;
+ unsigned i;
+ BITSET_FOREACH_SET(i, done->dependents, count) {
+ assert(instructions[i]->nr_dependencies);
- if (dest < node_count && BITSET_TEST(dependencies, dest))
- return false;
+ if (!(--instructions[i]->nr_dependencies))
+ BITSET_SET(worklist, i);
}
- /* Otherwise, we're good to go */
- return true;
+ free(done->dependents);
}
-/* Schedules, but does not emit, a single basic block. After scheduling, the
- * final tag and size of the block are known, which are necessary for branching
- * */
+/* While scheduling, we need to choose instructions satisfying certain
+ * criteria. As we schedule backwards, we choose the *last* instruction in the
+ * worklist to simulate in-order scheduling. Chosen instructions must satisfy a
+ * given predicate. */
-static midgard_bundle
-schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction *ins, int *skip)
-{
- int instructions_emitted = 0, packed_idx = 0;
- midgard_bundle bundle = { 0 };
+struct midgard_predicate {
+ /* TAG or ~0 for dont-care */
+ unsigned tag;
- midgard_instruction *scheduled[5] = { NULL };
+ /* True if we want to pop off the chosen instruction */
+ bool destructive;
- uint8_t tag = ins->type;
+ /* For ALU, choose only this unit */
+ unsigned unit;
- /* Default to the instruction's tag */
- bundle.tag = tag;
+ /* State for bundle constants. constants is the actual constants
+ * for the bundle. constant_count is the number of bytes (up to
+ * 16) currently in use for constants. When picking in destructive
+ * mode, the constants array will be updated, and the instruction
+ * will be adjusted to index into the constants array */
- switch (ins->type) {
- case TAG_ALU_4: {
- uint32_t control = 0;
- size_t bytes_emitted = sizeof(control);
+ midgard_constants *constants;
+ unsigned constant_mask;
+ bool blend_constant;
- /* TODO: Constant combining */
- int index = 0, last_unit = 0;
+ /* Exclude this destination (if not ~0) */
+ unsigned exclude;
- /* Previous instructions, for the purpose of parallelism */
- midgard_instruction *segment[4] = {0};
- int segment_size = 0;
+ /* Don't schedule instructions consuming conditionals (since we already
+ * scheduled one). Excludes conditional branches and csel */
+ bool no_cond;
- instructions_emitted = -1;
- midgard_instruction *pins = ins;
+ /* Require a minimal mask and (if nonzero) given destination. Used for
+ * writeout optimizations */
- unsigned constant_count = 0;
+ unsigned mask;
+ unsigned dest;
- for (;;) {
- midgard_instruction *ains = pins;
+ /* For load/store: how many pipeline registers are in use? The two
+ * scheduled instructions cannot use more than the 256-bits of pipeline
+ * space available or RA will fail (as it would run out of pipeline
+ * registers and fail to spill without breaking the schedule) */
- /* Advance instruction pointer */
- if (index) {
- ains = mir_next_op(pins);
- pins = ains;
- }
+ unsigned pipeline_count;
+};
- /* Out-of-work condition */
- if ((struct list_head *) ains == &block->instructions)
- break;
-
- /* Ensure that the chain can continue */
- if (ains->type != TAG_ALU_4) break;
-
- /* If there's already something in the bundle and we
- * have weird scheduler constraints, break now */
- if (ains->precede_break && index) break;
-
- /* According to the presentation "The ARM
- * Mali-T880 Mobile GPU" from HotChips 27,
- * there are two pipeline stages. Branching
- * position determined experimentally. Lines
- * are executed in parallel:
- *
- * [ VMUL ] [ SADD ]
- * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
- *
- * Verify that there are no ordering dependencies here.
- *
- * TODO: Allow for parallelism!!!
- */
+/* For an instruction that can fit, adjust it to fit and update the constants
+ * array, in destructive mode. Returns whether the fitting was successful. */
- /* Pick a unit for it if it doesn't force a particular unit */
+static bool
+mir_adjust_constants(midgard_instruction *ins,
+ struct midgard_predicate *pred,
+ bool destructive)
+{
+ /* Blend constants dominate */
+ if (ins->has_blend_constant) {
+ if (pred->constant_mask)
+ return false;
+ else if (destructive) {
+ pred->blend_constant = true;
+ pred->constant_mask = 0xffff;
+ return true;
+ }
+ }
- int unit = ains->unit;
+ /* No constant, nothing to adjust */
+ if (!ins->has_constants)
+ return true;
- if (!unit) {
- int op = ains->alu.op;
- int units = alu_opcode_props[op].props;
+ unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
+ midgard_reg_mode dst_mode = mir_typesize(ins);
- bool scalarable = units & UNITS_SCALAR;
- bool could_scalar = is_single_component_mask(ains->mask);
+ unsigned bundle_constant_mask = pred->constant_mask;
+ unsigned comp_mapping[2][16] = { };
+ uint8_t bundle_constants[16];
- /* Only 16/32-bit can run on a scalar unit */
- could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8;
- could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64;
- could_scalar &= ains->alu.dest_override == midgard_dest_override_none;
+ memcpy(bundle_constants, pred->constants, 16);
- if (ains->alu.reg_mode == midgard_reg_mode_16) {
- /* If we're running in 16-bit mode, we
- * can't have any 8-bit sources on the
- * scalar unit (since the scalar unit
- * doesn't understand 8-bit) */
+ /* Let's try to find a place for each active component of the constant
+ * register.
+ */
+ for (unsigned src = 0; src < 2; ++src) {
+ if (ins->src[src] != SSA_FIXED_REGISTER(REGISTER_CONSTANT))
+ continue;
- midgard_vector_alu_src s1 =
- vector_alu_from_unsigned(ains->alu.src1);
+ midgard_reg_mode src_mode = mir_srcsize(ins, src);
+ unsigned type_size = mir_bytes_for_mode(src_mode);
+ unsigned max_comp = 16 / type_size;
+ unsigned comp_mask = mir_from_bytemask(mir_bytemask_of_read_components_index(ins, src),
+ dst_mode);
+ unsigned type_mask = (1 << type_size) - 1;
- could_scalar &= !s1.half;
+ for (unsigned comp = 0; comp < max_comp; comp++) {
+ if (!(comp_mask & (1 << comp)))
+ continue;
- midgard_vector_alu_src s2 =
- vector_alu_from_unsigned(ains->alu.src2);
+ uint8_t *constantp = ins->constants.u8 + (type_size * comp);
+ unsigned best_reuse_bytes = 0;
+ signed best_place = -1;
+ unsigned i, j;
- could_scalar &= !s2.half;
- }
+ for (i = 0; i < 16; i += type_size) {
+ unsigned reuse_bytes = 0;
- bool scalar = could_scalar && scalarable;
-
- /* TODO: Check ahead-of-time for other scalar
- * hazards that otherwise get aborted out */
-
- if (scalar)
- assert(units & UNITS_SCALAR);
-
- if (!scalar) {
- if (last_unit >= UNIT_VADD) {
- if (units & UNIT_VLUT)
- unit = UNIT_VLUT;
- else
- break;
- } else {
- if ((units & UNIT_VMUL) && last_unit < UNIT_VMUL)
- unit = UNIT_VMUL;
- else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
- unit = UNIT_VADD;
- else if (units & UNIT_VLUT)
- unit = UNIT_VLUT;
- else
- break;
- }
- } else {
- if (last_unit >= UNIT_VADD) {
- if ((units & UNIT_SMUL) && !(control & UNIT_SMUL))
- unit = UNIT_SMUL;
- else if (units & UNIT_VLUT)
- unit = UNIT_VLUT;
- else
- break;
- } else {
- if ((units & UNIT_VMUL) && (last_unit < UNIT_VMUL))
- unit = UNIT_VMUL;
- else if ((units & UNIT_SADD) && !(control & UNIT_SADD) && !midgard_has_hazard(segment, segment_size, ains))
- unit = UNIT_SADD;
- else if (units & UNIT_VADD)
- unit = UNIT_VADD;
- else if (units & UNIT_SMUL)
- unit = UNIT_SMUL;
- else if (units & UNIT_VLUT)
- unit = UNIT_VLUT;
- else
- break;
- }
+ for (j = 0; j < type_size; j++) {
+ if (!(bundle_constant_mask & (1 << (i + j))))
+ continue;
+ if (constantp[j] != bundle_constants[i + j])
+ break;
+
+ reuse_bytes++;
}
- assert(unit & units);
+ /* Select the place where existing bytes can be
+ * reused so we leave empty slots to others
+ */
+ if (j == type_size &&
+ (reuse_bytes > best_reuse_bytes || best_place < 0)) {
+ best_reuse_bytes = reuse_bytes;
+ best_place = i;
+ break;
+ }
}
- /* Late unit check, this time for encoding (not parallelism) */
- if (unit <= last_unit) break;
+ /* This component couldn't fit in the remaining constant slot,
+ * no need check the remaining components, bail out now
+ */
+ if (best_place < 0)
+ return false;
- /* Clear the segment */
- if (last_unit < UNIT_VADD && unit >= UNIT_VADD)
- segment_size = 0;
+ memcpy(&bundle_constants[i], constantp, type_size);
+ bundle_constant_mask |= type_mask << best_place;
+ comp_mapping[src][comp] = best_place / type_size;
+ }
+ }
- if (midgard_has_hazard(segment, segment_size, ains))
- break;
+ /* If non-destructive, we're done */
+ if (!destructive)
+ return true;
- /* We're good to go -- emit the instruction */
- ains->unit = unit;
+ /* Otherwise update the constant_mask and constant values */
+ pred->constant_mask = bundle_constant_mask;
+ memcpy(pred->constants, bundle_constants, 16);
- segment[segment_size++] = ains;
+ /* Use comp_mapping as a swizzle */
+ mir_foreach_src(ins, s) {
+ if (ins->src[s] == r_constant)
+ mir_compose_swizzle(ins->swizzle[s], comp_mapping[s], ins->swizzle[s]);
+ }
- /* We try to reuse constants if possible, by adjusting
- * the swizzle */
+ return true;
+}
- if (ains->has_blend_constant) {
- /* Everything conflicts with the blend constant */
- if (bundle.has_embedded_constants)
- break;
+/* Conservative estimate of the pipeline registers required for load/store */
- bundle.has_blend_constant = 1;
- bundle.has_embedded_constants = 1;
- } else if (ains->has_constants && ains->alu.reg_mode == midgard_reg_mode_16) {
- /* TODO: DRY with the analysis pass */
+static unsigned
+mir_pipeline_count(midgard_instruction *ins)
+{
+ unsigned bytecount = 0;
- if (bundle.has_blend_constant)
- break;
+ mir_foreach_src(ins, i) {
+ /* Skip empty source */
+ if (ins->src[i] == ~0) continue;
- if (constant_count)
- break;
+ unsigned bytemask = mir_bytemask_of_read_components_index(ins, i);
- /* TODO: Fix packing XXX */
- uint16_t *bundles = (uint16_t *) bundle.constants;
- uint32_t *constants = (uint32_t *) ains->constants;
+ unsigned max = util_logbase2(bytemask) + 1;
+ bytecount += max;
+ }
- /* Copy them wholesale */
- for (unsigned i = 0; i < 4; ++i)
- bundles[i] = constants[i];
+ return DIV_ROUND_UP(bytecount, 16);
+}
- bundle.has_embedded_constants = true;
- constant_count = 4;
- } else if (ains->has_constants) {
- /* By definition, blend constants conflict with
- * everything, so if there are already
- * constants we break the bundle *now* */
+static midgard_instruction *
+mir_choose_instruction(
+ midgard_instruction **instructions,
+ BITSET_WORD *worklist, unsigned count,
+ struct midgard_predicate *predicate)
+{
+ /* Parse the predicate */
+ unsigned tag = predicate->tag;
+ bool alu = tag == TAG_ALU_4;
+ bool ldst = tag == TAG_LOAD_STORE_4;
+ unsigned unit = predicate->unit;
+ bool branch = alu && (unit == ALU_ENAB_BR_COMPACT);
+ bool scalar = (unit != ~0) && (unit & UNITS_SCALAR);
+ bool no_cond = predicate->no_cond;
+
+ unsigned mask = predicate->mask;
+ unsigned dest = predicate->dest;
+ bool needs_dest = mask & 0xF;
+
+ /* Iterate to find the best instruction satisfying the predicate */
+ unsigned i;
+
+ signed best_index = -1;
+ bool best_conditional = false;
+
+ /* Enforce a simple metric limiting distance to keep down register
+ * pressure. TOOD: replace with liveness tracking for much better
+ * results */
+
+ unsigned max_active = 0;
+ unsigned max_distance = 6;
+
+ BITSET_FOREACH_SET(i, worklist, count) {
+ max_active = MAX2(max_active, i);
+ }
- if (bundle.has_blend_constant)
- break;
+ BITSET_FOREACH_SET(i, worklist, count) {
+ if ((max_active - i) >= max_distance)
+ continue;
- /* For anything but blend constants, we can do
- * proper analysis, however */
+ if (tag != ~0 && instructions[i]->type != tag)
+ continue;
- /* TODO: Mask by which are used */
- uint32_t *constants = (uint32_t *) ains->constants;
- uint32_t *bundles = (uint32_t *) bundle.constants;
+ if (predicate->exclude != ~0 && instructions[i]->dest == predicate->exclude)
+ continue;
- uint32_t indices[4] = { 0 };
- bool break_bundle = false;
+ if (alu && !branch && !(alu_opcode_props[instructions[i]->alu.op].props & unit))
+ continue;
- for (unsigned i = 0; i < 4; ++i) {
- uint32_t cons = constants[i];
- bool constant_found = false;
+ if (branch && !instructions[i]->compact_branch)
+ continue;
- /* Search for the constant */
- for (unsigned j = 0; j < constant_count; ++j) {
- if (bundles[j] != cons)
- continue;
+ if (alu && scalar && !mir_is_scalar(instructions[i]))
+ continue;
- /* We found it, reuse */
- indices[i] = j;
- constant_found = true;
- break;
- }
+ if (alu && !mir_adjust_constants(instructions[i], predicate, false))
+ continue;
- if (constant_found)
- continue;
+ if (needs_dest && instructions[i]->dest != dest)
+ continue;
- /* We didn't find it, so allocate it */
- unsigned idx = constant_count++;
+ if (mask && ((~instructions[i]->mask) & mask))
+ continue;
- if (idx >= 4) {
- /* Uh-oh, out of space */
- break_bundle = true;
- break;
- }
+ if (ldst && mir_pipeline_count(instructions[i]) + predicate->pipeline_count > 2)
+ continue;
- /* We have space, copy it in! */
- bundles[idx] = cons;
- indices[i] = idx;
- }
+ bool conditional = alu && !branch && OP_IS_CSEL(instructions[i]->alu.op);
+ conditional |= (branch && instructions[i]->branch.conditional);
- if (break_bundle)
- break;
+ if (conditional && no_cond)
+ continue;
- /* Cool, we have it in. So use indices as a
- * swizzle */
+ /* Simulate in-order scheduling */
+ if ((signed) i < best_index)
+ continue;
- unsigned swizzle = SWIZZLE_FROM_ARRAY(indices);
- unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
+ best_index = i;
+ best_conditional = conditional;
+ }
- if (ains->ssa_args.src[0] == r_constant)
- ains->alu.src1 = vector_alu_apply_swizzle(ains->alu.src1, swizzle);
- if (ains->ssa_args.src[1] == r_constant)
- ains->alu.src2 = vector_alu_apply_swizzle(ains->alu.src2, swizzle);
+ /* Did we find anything? */
- bundle.has_embedded_constants = true;
- }
+ if (best_index < 0)
+ return NULL;
- if (ains->unit & UNITS_ANY_VECTOR) {
- bytes_emitted += sizeof(midgard_reg_info);
- bytes_emitted += sizeof(midgard_vector_alu);
- } else if (ains->compact_branch) {
- /* All of r0 has to be written out along with
- * the branch writeout */
-
- if (ains->writeout && !can_writeout_fragment(ctx, scheduled, index, ctx->temp_count)) {
- /* We only work on full moves
- * at the beginning. We could
- * probably do better */
- if (index != 0)
- break;
+ /* If we found something, remove it from the worklist */
+ assert(best_index < count);
- /* Inject a move */
- midgard_instruction ins = v_mov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
- ins.unit = UNIT_VMUL;
- control |= ins.unit;
-
- /* TODO don't leak */
- midgard_instruction *move =
- mem_dup(&ins, sizeof(midgard_instruction));
- bytes_emitted += sizeof(midgard_reg_info);
- bytes_emitted += sizeof(midgard_vector_alu);
- bundle.instructions[packed_idx++] = move;
- }
+ if (predicate->destructive) {
+ BITSET_CLEAR(worklist, best_index);
- if (ains->unit == ALU_ENAB_BRANCH) {
- bytes_emitted += sizeof(midgard_branch_extended);
- } else {
- bytes_emitted += sizeof(ains->br_compact);
- }
- } else {
- bytes_emitted += sizeof(midgard_reg_info);
- bytes_emitted += sizeof(midgard_scalar_alu);
- }
+ if (alu)
+ mir_adjust_constants(instructions[best_index], predicate, true);
- /* Defer marking until after writing to allow for break */
- scheduled[index] = ains;
- control |= ains->unit;
- last_unit = ains->unit;
- ++instructions_emitted;
- ++index;
- }
+ if (ldst)
+ predicate->pipeline_count += mir_pipeline_count(instructions[best_index]);
- int padding = 0;
+ /* Once we schedule a conditional, we can't again */
+ predicate->no_cond |= best_conditional;
+ }
- /* Pad ALU op to nearest word */
+ return instructions[best_index];
+}
- if (bytes_emitted & 15) {
- padding = 16 - (bytes_emitted & 15);
- bytes_emitted += padding;
- }
+/* Still, we don't choose instructions in a vacuum. We need a way to choose the
+ * best bundle type (ALU, load/store, texture). Nondestructive. */
- /* Constants must always be quadwords */
- if (bundle.has_embedded_constants)
- bytes_emitted += 16;
+static unsigned
+mir_choose_bundle(
+ midgard_instruction **instructions,
+ BITSET_WORD *worklist, unsigned count)
+{
+ /* At the moment, our algorithm is very simple - use the bundle of the
+ * best instruction, regardless of what else could be scheduled
+ * alongside it. This is not optimal but it works okay for in-order */
+
+ struct midgard_predicate predicate = {
+ .tag = ~0,
+ .destructive = false,
+ .exclude = ~0
+ };
- /* Size ALU instruction for tag */
- bundle.tag = (TAG_ALU_4) + (bytes_emitted / 16) - 1;
- bundle.padding = padding;
- bundle.control = bundle.tag | control;
+ midgard_instruction *chosen = mir_choose_instruction(instructions, worklist, count, &predicate);
- break;
- }
+ if (chosen)
+ return chosen->type;
+ else
+ return ~0;
+}
- case TAG_LOAD_STORE_4: {
- /* Load store instructions have two words at once. If
- * we only have one queued up, we need to NOP pad.
- * Otherwise, we store both in succession to save space
- * and cycles -- letting them go in parallel -- skip
- * the next. The usefulness of this optimisation is
- * greatly dependent on the quality of the instruction
- * scheduler.
- */
+/* We want to choose an ALU instruction filling a given unit */
+static void
+mir_choose_alu(midgard_instruction **slot,
+ midgard_instruction **instructions,
+ BITSET_WORD *worklist, unsigned len,
+ struct midgard_predicate *predicate,
+ unsigned unit)
+{
+ /* Did we already schedule to this slot? */
+ if ((*slot) != NULL)
+ return;
- midgard_instruction *next_op = mir_next_op(ins);
+ /* Try to schedule something, if not */
+ predicate->unit = unit;
+ *slot = mir_choose_instruction(instructions, worklist, len, predicate);
- if ((struct list_head *) next_op != &block->instructions && next_op->type == TAG_LOAD_STORE_4) {
- /* TODO: Concurrency check */
- instructions_emitted++;
- }
+ /* Store unit upon scheduling */
+ if (*slot && !((*slot)->compact_branch))
+ (*slot)->unit = unit;
+}
- break;
- }
+/* When we are scheduling a branch/csel, we need the consumed condition in the
+ * same block as a pipeline register. There are two options to enable this:
+ *
+ * - Move the conditional into the bundle. Preferred, but only works if the
+ * conditional is used only once and is from this block.
+ * - Copy the conditional.
+ *
+ * We search for the conditional. If it's in this block, single-use, and
+ * without embedded constants, we schedule it immediately. Otherwise, we
+ * schedule a move for it.
+ *
+ * mir_comparison_mobile is a helper to find the moveable condition.
+ */
- case TAG_TEXTURE_4: {
- /* Which tag we use depends on the shader stage */
- bool in_frag = ctx->stage == MESA_SHADER_FRAGMENT;
- bundle.tag = in_frag ? TAG_TEXTURE_4 : TAG_TEXTURE_4_VTX;
- break;
- }
+static unsigned
+mir_comparison_mobile(
+ compiler_context *ctx,
+ midgard_instruction **instructions,
+ struct midgard_predicate *predicate,
+ unsigned count,
+ unsigned cond)
+{
+ if (!mir_single_use(ctx, cond))
+ return ~0;
- default:
- unreachable("Unknown tag");
- break;
- }
+ unsigned ret = ~0;
- /* Copy the instructions into the bundle */
- bundle.instruction_count = instructions_emitted + 1 + packed_idx;
+ for (unsigned i = 0; i < count; ++i) {
+ if (instructions[i]->dest != cond)
+ continue;
- midgard_instruction *uins = ins;
- for (; packed_idx < bundle.instruction_count; ++packed_idx) {
- bundle.instructions[packed_idx] = uins;
- uins = mir_next_op(uins);
- }
+ /* Must fit in an ALU bundle */
+ if (instructions[i]->type != TAG_ALU_4)
+ return ~0;
- *skip = instructions_emitted;
+ /* If it would itself require a condition, that's recursive */
+ if (OP_IS_CSEL(instructions[i]->alu.op))
+ return ~0;
- return bundle;
-}
+ /* We'll need to rewrite to .w but that doesn't work for vector
+ * ops that don't replicate (ball/bany), so bail there */
-/* Schedule a single block by iterating its instruction to create bundles.
- * While we go, tally about the bundle sizes to compute the block size. */
+ if (GET_CHANNEL_COUNT(alu_opcode_props[instructions[i]->alu.op].props))
+ return ~0;
-static void
-schedule_block(compiler_context *ctx, midgard_block *block)
-{
- util_dynarray_init(&block->bundles, NULL);
+ /* Ensure it will fit with constants */
- block->quadword_count = 0;
+ if (!mir_adjust_constants(instructions[i], predicate, false))
+ return ~0;
- mir_foreach_instr_in_block(block, ins) {
- int skip;
- midgard_bundle bundle = schedule_bundle(ctx, block, ins, &skip);
- util_dynarray_append(&block->bundles, midgard_bundle, bundle);
+ /* Ensure it is written only once */
- if (bundle.has_blend_constant) {
- /* TODO: Multiblock? */
- int quadwords_within_block = block->quadword_count + quadword_size(bundle.tag) - 1;
- ctx->blend_constant_offset = quadwords_within_block * 0x10;
- }
+ if (ret != ~0)
+ return ~0;
+ else
+ ret = i;
+ }
+
+ /* Inject constants now that we are sure we want to */
+ if (ret != ~0)
+ mir_adjust_constants(instructions[ret], predicate, true);
- while(skip--)
- ins = mir_next_op(ins);
+ return ret;
+}
- block->quadword_count += quadword_size(bundle.tag);
+/* Using the information about the moveable conditional itself, we either pop
+ * that condition off the worklist for use now, or create a move to
+ * artificially schedule instead as a fallback */
+
+static midgard_instruction *
+mir_schedule_comparison(
+ compiler_context *ctx,
+ midgard_instruction **instructions,
+ struct midgard_predicate *predicate,
+ BITSET_WORD *worklist, unsigned count,
+ unsigned cond, bool vector, unsigned *swizzle,
+ midgard_instruction *user)
+{
+ /* TODO: swizzle when scheduling */
+ unsigned comp_i =
+ (!vector && (swizzle[0] == 0)) ?
+ mir_comparison_mobile(ctx, instructions, predicate, count, cond) : ~0;
+
+ /* If we can, schedule the condition immediately */
+ if ((comp_i != ~0) && BITSET_TEST(worklist, comp_i)) {
+ assert(comp_i < count);
+ BITSET_CLEAR(worklist, comp_i);
+ return instructions[comp_i];
}
- block->is_scheduled = true;
-}
+ /* Otherwise, we insert a move */
-/* The following passes reorder MIR instructions to enable better scheduling */
+ midgard_instruction mov = v_mov(cond, cond);
+ mov.mask = vector ? 0xF : 0x1;
+ memcpy(mov.swizzle[1], swizzle, sizeof(mov.swizzle[1]));
-static void
-midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
-{
- mir_foreach_instr_in_block_safe(block, ins) {
- if (ins->type != TAG_LOAD_STORE_4) continue;
-
- /* We've found a load/store op. Check if next is also load/store. */
- midgard_instruction *next_op = mir_next_op(ins);
- if (&next_op->link != &block->instructions) {
- if (next_op->type == TAG_LOAD_STORE_4) {
- /* If so, we're done since we're a pair */
- ins = mir_next_op(ins);
- continue;
- }
+ return mir_insert_instruction_before(ctx, user, mov);
+}
- /* Maximum search distance to pair, to avoid register pressure disasters */
- int search_distance = 8;
+/* Most generally, we need instructions writing to r31 in the appropriate
+ * components */
- /* Otherwise, we have an orphaned load/store -- search for another load */
- mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
- /* Terminate search if necessary */
- if (!(search_distance--)) break;
+static midgard_instruction *
+mir_schedule_condition(compiler_context *ctx,
+ struct midgard_predicate *predicate,
+ BITSET_WORD *worklist, unsigned count,
+ midgard_instruction **instructions,
+ midgard_instruction *last)
+{
+ /* For a branch, the condition is the only argument; for csel, third */
+ bool branch = last->compact_branch;
+ unsigned condition_index = branch ? 0 : 2;
- if (c->type != TAG_LOAD_STORE_4) continue;
+ /* csel_v is vector; otherwise, conditions are scalar */
+ bool vector = !branch && OP_IS_CSEL_V(last->alu.op);
- /* Stores cannot be reordered, since they have
- * dependencies. For the same reason, indirect
- * loads cannot be reordered as their index is
- * loaded in r27.w */
+ /* Grab the conditional instruction */
- if (OP_IS_STORE(c->load_store.op)) continue;
+ midgard_instruction *cond = mir_schedule_comparison(
+ ctx, instructions, predicate, worklist, count, last->src[condition_index],
+ vector, last->swizzle[2], last);
- /* It appears the 0x8 bit is set whenever a
- * load is direct, unset when it is indirect.
- * Skip indirect loads. */
+ /* We have exclusive reign over this (possibly move) conditional
+ * instruction. We can rewrite into a pipeline conditional register */
- if (!(c->load_store.arg_2 & 0x8)) continue;
+ predicate->exclude = cond->dest;
+ cond->dest = SSA_FIXED_REGISTER(31);
- /* We found one! Move it up to pair and remove it from the old location */
+ if (!vector) {
+ cond->mask = (1 << COMPONENT_W);
- mir_insert_instruction_before(ins, *c);
- mir_remove_instruction(c);
+ mir_foreach_src(cond, s) {
+ if (cond->src[s] == ~0)
+ continue;
- break;
- }
+ for (unsigned q = 0; q < 4; ++q)
+ cond->swizzle[s][q + COMPONENT_W] = cond->swizzle[s][q];
}
}
+
+ /* Schedule the unit: csel is always in the latter pipeline, so a csel
+ * condition must be in the former pipeline stage (vmul/sadd),
+ * depending on scalar/vector of the instruction itself. A branch must
+ * be written from the latter pipeline stage and a branch condition is
+ * always scalar, so it is always in smul (exception: ball/bany, which
+ * will be vadd) */
+
+ if (branch)
+ cond->unit = UNIT_SMUL;
+ else
+ cond->unit = vector ? UNIT_VMUL : UNIT_SADD;
+
+ return cond;
}
-/* When we're 'squeezing down' the values in the IR, we maintain a hash
- * as such */
+/* Schedules a single bundle of the given type */
-static unsigned
-find_or_allocate_temp(compiler_context *ctx, unsigned hash)
+static midgard_bundle
+mir_schedule_texture(
+ midgard_instruction **instructions,
+ BITSET_WORD *worklist, unsigned len)
{
- if ((hash < 0) || (hash >= SSA_FIXED_MINIMUM))
- return hash;
-
- unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(
- ctx->hash_to_temp, hash + 1);
+ struct midgard_predicate predicate = {
+ .tag = TAG_TEXTURE_4,
+ .destructive = true,
+ .exclude = ~0
+ };
- if (temp)
- return temp - 1;
+ midgard_instruction *ins =
+ mir_choose_instruction(instructions, worklist, len, &predicate);
- /* If no temp is find, allocate one */
- temp = ctx->temp_count++;
- ctx->max_hash = MAX2(ctx->max_hash, hash);
+ mir_update_worklist(worklist, len, instructions, ins);
- _mesa_hash_table_u64_insert(ctx->hash_to_temp,
- hash + 1, (void *) ((uintptr_t) temp + 1));
+ struct midgard_bundle out = {
+ .tag = ins->texture.op == TEXTURE_OP_BARRIER ?
+ TAG_TEXTURE_4_BARRIER : TAG_TEXTURE_4,
+ .instruction_count = 1,
+ .instructions = { ins }
+ };
- return temp;
+ return out;
}
-/* Reassigns numbering to get rid of gaps in the indices */
-
-static void
-mir_squeeze_index(compiler_context *ctx)
+static midgard_bundle
+mir_schedule_ldst(
+ midgard_instruction **instructions,
+ BITSET_WORD *worklist, unsigned len)
{
- /* Reset */
- ctx->temp_count = 0;
- /* TODO don't leak old hash_to_temp */
- ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
+ struct midgard_predicate predicate = {
+ .tag = TAG_LOAD_STORE_4,
+ .destructive = true,
+ .exclude = ~0
+ };
- mir_foreach_instr_global(ctx, ins) {
- ins->ssa_args.dest = find_or_allocate_temp(ctx, ins->ssa_args.dest);
+ /* Try to pick two load/store ops. Second not gauranteed to exist */
- for (unsigned i = 0; i < ARRAY_SIZE(ins->ssa_args.src); ++i)
- ins->ssa_args.src[i] = find_or_allocate_temp(ctx, ins->ssa_args.src[i]);
- }
+ midgard_instruction *ins =
+ mir_choose_instruction(instructions, worklist, len, &predicate);
+
+ midgard_instruction *pair =
+ mir_choose_instruction(instructions, worklist, len, &predicate);
+
+ struct midgard_bundle out = {
+ .tag = TAG_LOAD_STORE_4,
+ .instruction_count = pair ? 2 : 1,
+ .instructions = { ins, pair }
+ };
+
+ /* We have to update the worklist atomically, since the two
+ * instructions run concurrently (TODO: verify it's not pipelined) */
+
+ mir_update_worklist(worklist, len, instructions, ins);
+ mir_update_worklist(worklist, len, instructions, pair);
+
+ return out;
}
-static midgard_instruction
-v_load_store_scratch(
- unsigned srcdest,
- unsigned index,
- bool is_store,
- unsigned mask)
+static midgard_bundle
+mir_schedule_alu(
+ compiler_context *ctx,
+ midgard_instruction **instructions,
+ BITSET_WORD *worklist, unsigned len)
{
- /* We index by 32-bit vec4s */
- unsigned byte = (index * 4 * 4);
-
- midgard_instruction ins = {
- .type = TAG_LOAD_STORE_4,
- .mask = mask,
- .ssa_args = {
- .dest = -1,
- .src = { -1, -1, -1 },
- },
- .load_store = {
- .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
- .swizzle = SWIZZLE_XYZW,
-
- /* For register spilling - to thread local storage */
- .arg_1 = 0xEA,
- .arg_2 = 0x1E,
-
- /* Splattered across, TODO combine logically */
- .varying_parameters = (byte & 0x1FF) << 1,
- .address = (byte >> 9)
- }
+ struct midgard_bundle bundle = {};
+
+ unsigned bytes_emitted = sizeof(bundle.control);
+
+ struct midgard_predicate predicate = {
+ .tag = TAG_ALU_4,
+ .destructive = true,
+ .exclude = ~0,
+ .constants = &bundle.constants
};
- if (is_store) {
- /* r0 = r26, r1 = r27 */
- assert(srcdest == SSA_FIXED_REGISTER(26) || srcdest == SSA_FIXED_REGISTER(27));
- ins.ssa_args.src[0] = (srcdest == SSA_FIXED_REGISTER(27)) ? SSA_FIXED_REGISTER(1) : SSA_FIXED_REGISTER(0);
+ midgard_instruction *vmul = NULL;
+ midgard_instruction *vadd = NULL;
+ midgard_instruction *vlut = NULL;
+ midgard_instruction *smul = NULL;
+ midgard_instruction *sadd = NULL;
+ midgard_instruction *branch = NULL;
+
+ mir_choose_alu(&branch, instructions, worklist, len, &predicate, ALU_ENAB_BR_COMPACT);
+ mir_update_worklist(worklist, len, instructions, branch);
+ bool writeout = branch && branch->writeout;
+ bool zs_writeout = writeout && (branch->writeout_depth | branch->writeout_stencil);
+
+ if (branch && branch->branch.conditional) {
+ midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);
+
+ if (cond->unit == UNIT_VADD)
+ vadd = cond;
+ else if (cond->unit == UNIT_SMUL)
+ smul = cond;
+ else
+ unreachable("Bad condition");
+ }
+
+ /* If we have a render target reference, schedule a move for it. Since
+ * this will be in sadd, we boost this to prevent scheduling csel into
+ * smul */
+
+ if (writeout && (branch->constants.u32[0] || ctx->is_blend)) {
+ sadd = ralloc(ctx, midgard_instruction);
+ *sadd = v_mov(~0, make_compiler_temp(ctx));
+ sadd->unit = UNIT_SADD;
+ sadd->mask = 0x1;
+ sadd->has_inline_constant = true;
+ sadd->inline_constant = branch->constants.u32[0];
+ branch->src[1] = sadd->dest;
+ branch->src_types[1] = sadd->dest_type;
+
+ /* Mask off any conditionals. Could be optimized to just scalar
+ * conditionals TODO */
+ predicate.no_cond = true;
+ }
+
+ mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
+
+ if (!writeout) {
+ mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT);
} else {
- ins.ssa_args.dest = srcdest;
+ /* Propagate up */
+ bundle.last_writeout = branch->last_writeout;
}
- return ins;
-}
+ if (writeout && !zs_writeout) {
+ vadd = ralloc(ctx, midgard_instruction);
+ *vadd = v_mov(~0, make_compiler_temp(ctx));
-void
-schedule_program(compiler_context *ctx)
-{
- struct ra_graph *g = NULL;
- bool spilled = false;
- int iter_count = 1000; /* max iterations */
+ if (!ctx->is_blend) {
+ vadd->alu.op = midgard_alu_op_iadd;
+ vadd->src[0] = SSA_FIXED_REGISTER(31);
+ vadd->src_types[0] = nir_type_uint32;
- /* Number of 128-bit slots in memory we've spilled into */
- unsigned spill_count = 0;
+ for (unsigned c = 0; c < 16; ++c)
+ vadd->swizzle[0][c] = COMPONENT_X;
- midgard_promote_uniforms(ctx, 8);
+ vadd->has_inline_constant = true;
+ vadd->inline_constant = 0;
+ } else {
+ vadd->src[1] = SSA_FIXED_REGISTER(1);
+ vadd->src_types[0] = nir_type_uint32;
+
+ for (unsigned c = 0; c < 16; ++c)
+ vadd->swizzle[1][c] = COMPONENT_W;
+ }
- mir_foreach_block(ctx, block) {
- midgard_pair_load_store(ctx, block);
+ vadd->unit = UNIT_VADD;
+ vadd->mask = 0x1;
+ branch->src[2] = vadd->dest;
+ branch->src_types[2] = vadd->dest_type;
}
- /* Must be lowered right before RA */
- mir_squeeze_index(ctx);
- mir_lower_special_reads(ctx);
+ mir_choose_alu(&vadd, instructions, worklist, len, &predicate, UNIT_VADD);
+
+ mir_update_worklist(worklist, len, instructions, vlut);
+ mir_update_worklist(worklist, len, instructions, vadd);
+ mir_update_worklist(worklist, len, instructions, smul);
+
+ bool vadd_csel = vadd && OP_IS_CSEL(vadd->alu.op);
+ bool smul_csel = smul && OP_IS_CSEL(smul->alu.op);
+
+ if (vadd_csel || smul_csel) {
+ midgard_instruction *ins = vadd_csel ? vadd : smul;
+ midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, ins);
+
+ if (cond->unit == UNIT_VMUL)
+ vmul = cond;
+ else if (cond->unit == UNIT_SADD)
+ sadd = cond;
+ else
+ unreachable("Bad condition");
+ }
- /* Lowering can introduce some dead moves */
+ /* Stage 2, let's schedule sadd before vmul for writeout */
+ mir_choose_alu(&sadd, instructions, worklist, len, &predicate, UNIT_SADD);
- mir_foreach_block(ctx, block) {
- midgard_opt_dead_move_eliminate(ctx, block);
- }
+ /* Check if writeout reads its own register */
- do {
- /* If we spill, find the best spill node and spill it */
+ if (writeout) {
+ midgard_instruction *stages[] = { sadd, vadd, smul };
+ unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(zs_writeout ? 1 : 0) : branch->src[0];
+ unsigned writeout_mask = 0x0;
+ bool bad_writeout = false;
- unsigned spill_index = ctx->temp_count;
- if (g && spilled) {
- /* All nodes are equal in spill cost, but we can't
- * spill nodes written to from an unspill */
+ for (unsigned i = 0; i < ARRAY_SIZE(stages); ++i) {
+ if (!stages[i])
+ continue;
- for (unsigned i = 0; i < ctx->temp_count; ++i) {
- ra_set_node_spill_cost(g, i, 1.0);
- }
+ if (stages[i]->dest != src)
+ continue;
- mir_foreach_instr_global(ctx, ins) {
- if (ins->type != TAG_LOAD_STORE_4) continue;
- if (ins->load_store.op != midgard_op_ld_int4) continue;
- if (ins->load_store.arg_1 != 0xEA) continue;
- if (ins->load_store.arg_2 != 0x1E) continue;
- ra_set_node_spill_cost(g, ins->ssa_args.dest, -1.0);
+ writeout_mask |= stages[i]->mask;
+ bad_writeout |= mir_has_arg(stages[i], branch->src[0]);
+ }
+
+ /* It's possible we'll be able to schedule something into vmul
+ * to fill r0/r1. Let's peak into the future, trying to schedule
+ * vmul specially that way. */
+
+ unsigned full_mask = zs_writeout ?
+ (1 << (branch->writeout_depth + branch->writeout_stencil)) - 1 :
+ 0xF;
+
+ if (!bad_writeout && writeout_mask != full_mask) {
+ predicate.unit = UNIT_VMUL;
+ predicate.dest = src;
+ predicate.mask = writeout_mask ^ full_mask;
+
+ struct midgard_instruction *peaked =
+ mir_choose_instruction(instructions, worklist, len, &predicate);
+
+ if (peaked) {
+ vmul = peaked;
+ vmul->unit = UNIT_VMUL;
+ writeout_mask |= predicate.mask;
+ assert(writeout_mask == full_mask);
}
- int spill_node = ra_get_best_spill_node(g);
+ /* Cleanup */
+ predicate.dest = predicate.mask = 0;
+ }
+
+ /* Finally, add a move if necessary */
+ if (bad_writeout || writeout_mask != full_mask) {
+ unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(zs_writeout ? 1 : 0) : make_compiler_temp(ctx);
+
+ vmul = ralloc(ctx, midgard_instruction);
+ *vmul = v_mov(src, temp);
+ vmul->unit = UNIT_VMUL;
+ vmul->mask = full_mask ^ writeout_mask;
+
+ /* Rewrite to use our temp */
- if (spill_node < 0) {
- mir_print_shader(ctx);
- assert(0);
+ for (unsigned i = 0; i < ARRAY_SIZE(stages); ++i) {
+ if (stages[i])
+ mir_rewrite_index_dst_single(stages[i], src, temp);
}
- /* Check the class. Work registers legitimately spill
- * to TLS, but special registers just spill to work
- * registers */
- unsigned class = ra_get_node_class(g, spill_node);
- bool is_special = (class >> 2) != REG_CLASS_WORK;
- bool is_special_w = (class >> 2) == REG_CLASS_TEXW;
+ mir_rewrite_index_src_single(branch, src, temp);
+ }
+ }
- /* Allocate TLS slot (maybe) */
- unsigned spill_slot = !is_special ? spill_count++ : 0;
- midgard_instruction *spill_move = NULL;
+ mir_choose_alu(&vmul, instructions, worklist, len, &predicate, UNIT_VMUL);
- /* For TLS, replace all stores to the spilled node. For
- * special reads, just keep as-is; the class will be demoted
- * implicitly. For special writes, spill to a work register */
+ mir_update_worklist(worklist, len, instructions, vmul);
+ mir_update_worklist(worklist, len, instructions, sadd);
- if (!is_special || is_special_w) {
- mir_foreach_instr_global_safe(ctx, ins) {
- if (ins->ssa_args.dest != spill_node) continue;
+ bundle.has_blend_constant = predicate.blend_constant;
+ bundle.has_embedded_constants = predicate.constant_mask != 0;
- midgard_instruction st;
+ unsigned padding = 0;
- if (is_special_w) {
- spill_slot = spill_index++;
- st = v_mov(spill_node, blank_alu_src, spill_slot);
- } else {
- ins->ssa_args.dest = SSA_FIXED_REGISTER(26);
- st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
- }
+ /* Now that we have finished scheduling, build up the bundle */
+ midgard_instruction *stages[] = { vmul, sadd, vadd, smul, vlut, branch };
- spill_move = mir_insert_instruction_before(mir_next_op(ins), st);
+ for (unsigned i = 0; i < ARRAY_SIZE(stages); ++i) {
+ if (stages[i]) {
+ bundle.control |= stages[i]->unit;
+ bytes_emitted += bytes_for_instruction(stages[i]);
+ bundle.instructions[bundle.instruction_count++] = stages[i];
- if (!is_special)
- ctx->spills++;
- }
- }
+ /* If we branch, we can't spill to TLS since the store
+ * instruction will never get executed. We could try to
+ * break the bundle but this is probably easier for
+ * now. */
- /* Insert a load from TLS before the first consecutive
- * use of the node, rewriting to use spilled indices to
- * break up the live range. Or, for special, insert a
- * move. Ironically the latter *increases* register
- * pressure, but the two uses of the spilling mechanism
- * are somewhat orthogonal. (special spilling is to use
- * work registers to back special registers; TLS
- * spilling is to use memory to back work registers) */
-
- mir_foreach_block(ctx, block) {
-
- bool consecutive_skip = false;
- unsigned consecutive_index = 0;
-
- mir_foreach_instr_in_block(block, ins) {
- /* We can't rewrite the move used to spill in the first place */
- if (ins == spill_move) continue;
-
- if (!mir_has_arg(ins, spill_node)) {
- consecutive_skip = false;
- continue;
- }
+ if (branch)
+ stages[i]->no_spill |= (1 << REG_CLASS_WORK);
+ }
+ }
- if (consecutive_skip) {
- /* Rewrite */
- mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
- continue;
- }
+ /* Pad ALU op to nearest word */
- if (!is_special_w) {
- consecutive_index = ++spill_index;
+ if (bytes_emitted & 15) {
+ padding = 16 - (bytes_emitted & 15);
+ bytes_emitted += padding;
+ }
- midgard_instruction *before = ins;
+ /* Constants must always be quadwords */
+ if (bundle.has_embedded_constants)
+ bytes_emitted += 16;
- /* For a csel, go back one more not to break up the bundle */
- if (ins->type == TAG_ALU_4 && OP_IS_CSEL(ins->alu.op))
- before = mir_prev_op(before);
+ /* Size ALU instruction for tag */
+ bundle.tag = (TAG_ALU_4) + (bytes_emitted / 16) - 1;
- midgard_instruction st;
+ /* MRT capable GPUs use a special writeout procedure */
+ if (writeout && !(ctx->quirks & MIDGARD_NO_UPPER_ALU))
+ bundle.tag += 4;
- if (is_special) {
- /* Move */
- st = v_mov(spill_node, blank_alu_src, consecutive_index);
- } else {
- /* TLS load */
- st = v_load_store_scratch(consecutive_index, spill_slot, false, 0xF);
- }
+ bundle.padding = padding;
+ bundle.control |= bundle.tag;
- mir_insert_instruction_before(before, st);
- // consecutive_skip = true;
- } else {
- /* Special writes already have their move spilled in */
- consecutive_index = spill_slot;
- }
+ return bundle;
+}
+/* Schedule a single block by iterating its instruction to create bundles.
+ * While we go, tally about the bundle sizes to compute the block size. */
- /* Rewrite to use */
- mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
- if (!is_special)
- ctx->fills++;
- }
- }
- }
+static void
+schedule_block(compiler_context *ctx, midgard_block *block)
+{
+ /* Copy list to dynamic array */
+ unsigned len = 0;
+ midgard_instruction **instructions = flatten_mir(block, &len);
+
+ if (!len)
+ return;
+
+ /* Calculate dependencies and initial worklist */
+ unsigned node_count = ctx->temp_count + 1;
+ mir_create_dependency_graph(instructions, len, node_count);
- mir_squeeze_index(ctx);
+ /* Allocate the worklist */
+ size_t sz = BITSET_WORDS(len) * sizeof(BITSET_WORD);
+ BITSET_WORD *worklist = calloc(sz, 1);
+ mir_initialize_worklist(worklist, instructions, len);
- g = NULL;
- g = allocate_registers(ctx, &spilled);
- } while(spilled && ((iter_count--) > 0));
+ struct util_dynarray bundles;
+ util_dynarray_init(&bundles, NULL);
+
+ block->quadword_count = 0;
+ unsigned blend_offset = 0;
- /* We can simplify a bit after RA */
+ for (;;) {
+ unsigned tag = mir_choose_bundle(instructions, worklist, len);
+ midgard_bundle bundle;
- mir_foreach_block(ctx, block) {
- midgard_opt_post_move_eliminate(ctx, block, g);
+ if (tag == TAG_TEXTURE_4)
+ bundle = mir_schedule_texture(instructions, worklist, len);
+ else if (tag == TAG_LOAD_STORE_4)
+ bundle = mir_schedule_ldst(instructions, worklist, len);
+ else if (tag == TAG_ALU_4)
+ bundle = mir_schedule_alu(ctx, instructions, worklist, len);
+ else
+ break;
+
+ util_dynarray_append(&bundles, midgard_bundle, bundle);
+
+ if (bundle.has_blend_constant)
+ blend_offset = block->quadword_count;
+
+ block->quadword_count += midgard_tag_props[bundle.tag].size;
}
- /* After RA finishes, we schedule all at once */
+ /* We emitted bundles backwards; copy into the block in reverse-order */
- mir_foreach_block(ctx, block) {
- schedule_block(ctx, block);
+ util_dynarray_init(&block->bundles, block);
+ util_dynarray_foreach_reverse(&bundles, midgard_bundle, bundle) {
+ util_dynarray_append(&block->bundles, midgard_bundle, *bundle);
}
+ util_dynarray_fini(&bundles);
- /* Finally, we create pipeline registers as a peephole pass after
- * scheduling. This isn't totally optimal, since there are cases where
- * the usage of pipeline registers can eliminate spills, but it does
- * save some power */
+ /* Blend constant was backwards as well. blend_offset if set is
+ * strictly positive, as an offset of zero would imply constants before
+ * any instructions which is invalid in Midgard. TODO: blend constants
+ * are broken if you spill since then quadword_count becomes invalid
+ * XXX */
- mir_create_pipeline_registers(ctx);
+ if (blend_offset)
+ ctx->blend_constant_offset = ((ctx->quadword_count + block->quadword_count) - blend_offset - 1) * 0x10;
- if (iter_count <= 0) {
- fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");
- assert(0);
+ block->scheduled = true;
+ ctx->quadword_count += block->quadword_count;
+
+ /* Reorder instructions to match bundled. First remove existing
+ * instructions and then recreate the list */
+
+ mir_foreach_instr_in_block_safe(block, ins) {
+ list_del(&ins->link);
+ }
+
+ mir_foreach_instr_in_block_scheduled_rev(block, ins) {
+ list_add(&ins->link, &block->base.instructions);
}
- /* Report spilling information. spill_count is in 128-bit slots (vec4 x
- * fp32), but tls_size is in bytes, so multiply by 16 */
+ free(instructions); /* Allocated by flatten_mir() */
+ free(worklist);
+}
+
+void
+midgard_schedule_program(compiler_context *ctx)
+{
+ midgard_promote_uniforms(ctx);
+
+ /* Must be lowered right before scheduling */
+ mir_squeeze_index(ctx);
+ mir_lower_special_reads(ctx);
+ mir_squeeze_index(ctx);
- ctx->tls_size = spill_count * 16;
+ /* Lowering can introduce some dead moves */
+
+ mir_foreach_block(ctx, _block) {
+ midgard_block *block = (midgard_block *) _block;
+ midgard_opt_dead_move_eliminate(ctx, block);
+ schedule_block(ctx, block);
+ }
- install_registers(ctx, g);
}