pan/midgard: Remove undefined behavior

[mesa.git] / src / panfrost / midgard / midgard_schedule.c

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index 2e794687e6614f470ffa4e06d08ca5dd96bcb609..d05bdf79d4782715f66d7cc3e4dbd289e41ff925 100644 (file)
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -165,6 +165,9 @@ mir_create_dependency_graph(midgard_instruction **instructions, unsigned count,
                 util_dynarray_fini(&last_read[i]);
                 util_dynarray_fini(&last_write[i]);
         }
+
+        free(last_read);
+        free(last_write);
 }
 
 /* Does the mask cover more than a scalar? */
@@ -369,7 +372,7 @@ mir_adjust_constants(midgard_instruction *ins,
         if (!ins->has_constants)
                 return true;
 
-        if (ins->alu.reg_mode == midgard_reg_mode_16) {
+        if (ins->alu.reg_mode != midgard_reg_mode_32) {
                 /* TODO: 16-bit constant combining */
                 if (pred->constant_count)
                         return false;
@@ -1091,6 +1094,9 @@ schedule_block(compiler_context *ctx, midgard_block *block)
         mir_foreach_instr_in_block_scheduled_rev(block, ins) {
                 list_add(&ins->link, &block->instructions);
         }
+
+       free(instructions); /* Allocated by flatten_mir() */
+       free(worklist);
 }
 
 /* When we're 'squeezing down' the values in the IR, we maintain a hash
@@ -1169,16 +1175,14 @@ v_load_store_scratch(
                         /* For register spilling - to thread local storage */
                         .arg_1 = 0xEA,
                         .arg_2 = 0x1E,
-
-                        /* Splattered across, TODO combine logically */
-                        .varying_parameters = (byte & 0x1FF) << 1,
-                        .address = (byte >> 9)
                 },
 
                 /* If we spill an unspill, RA goes into an infinite loop */
                 .no_spill = true
         };
 
+        ins.constants[0] = byte;
+
        if (is_store) {
                 /* r0 = r26, r1 = r27 */
                 assert(srcdest == SSA_FIXED_REGISTER(26) || srcdest == SSA_FIXED_REGISTER(27));
@@ -1388,6 +1392,8 @@ static void mir_spill_register(
         mir_foreach_instr_global(ctx, ins) {
                 ins->hint = false;
         }
+
+        free(cost);
 }
 
 void
@@ -1423,7 +1429,11 @@ schedule_program(compiler_context *ctx)
                 mir_squeeze_index(ctx);
                 mir_invalidate_liveness(ctx);
 
-                l = NULL;
+                if (l) {
+                        lcra_free(l);
+                        l = NULL;
+                }
+
                 l = allocate_registers(ctx, &spilled);
         } while(spilled && ((iter_count--) > 0));
 
@@ -1438,4 +1448,6 @@ schedule_program(compiler_context *ctx)
         ctx->tls_size = spill_count * 16;
 
         install_registers(ctx, l);
+
+        lcra_free(l);
 }