void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new)
{
- if (ins->ssa_args.src0 == old)
- ins->ssa_args.src0 = new;
+ for (unsigned i = 0; i < ARRAY_SIZE(ins->ssa_args.src); ++i) {
+ if (ins->ssa_args.src[i] == old)
+ ins->ssa_args.src[i] = new;
+ }
+}
- if (ins->ssa_args.src1 == old &&
- !ins->ssa_args.inline_constant)
- ins->ssa_args.src1 = new;
+void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new)
+{
+ if (ins->ssa_args.dest == old)
+ ins->ssa_args.dest = new;
}
static unsigned
return s.swizzle;
} else if (ins->type == TAG_LOAD_STORE_4) {
- assert(idx == 0);
- return ins->load_store.swizzle;
+ /* Main swizzle of a load is on the destination */
+ if (!OP_IS_STORE(ins->load_store.op))
+ idx++;
+
+ switch (idx) {
+ case 0:
+ return ins->load_store.swizzle;
+ case 1:
+ case 2: {
+ uint8_t raw =
+ (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
+
+ return component_to_swizzle(midgard_ldst_select(raw).component);
+ }
+ default:
+ unreachable("Unknown load/store source");
+ }
} else if (ins->type == TAG_TEXTURE_4) {
switch (idx) {
case 0:
else
ins->alu.src2 = pack;
} else if (ins->type == TAG_LOAD_STORE_4) {
- ins->load_store.swizzle = new;
+ /* Main swizzle of a load is on the destination */
+ if (!OP_IS_STORE(ins->load_store.op))
+ idx++;
+
+ switch (idx) {
+ case 0:
+ ins->load_store.swizzle = new;
+ break;
+ case 1:
+ case 2: {
+ uint8_t raw =
+ (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
+
+ midgard_ldst_register_select sel
+ = midgard_ldst_select(raw);
+ sel.component = swizzle_to_component(new);
+ uint8_t packed = midgard_ldst_pack(sel);
+
+ if (idx == 2)
+ ins->load_store.arg_2 = packed;
+ else
+ ins->load_store.arg_1 = packed;
+
+ break;
+ }
+ default:
+ assert(new == 0);
+ break;
+ }
} else if (ins->type == TAG_TEXTURE_4) {
switch (idx) {
case 0:
static void
mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned swizzle)
{
- if (ins->ssa_args.src0 == old) {
- ins->ssa_args.src0 = new;
-
- mir_set_swizzle(ins, 0,
- pan_compose_swizzle(mir_get_swizzle(ins, 0), swizzle));
- }
+ for (unsigned i = 0; i < ARRAY_SIZE(ins->ssa_args.src); ++i) {
+ if (ins->ssa_args.src[i] != old) continue;
- if (ins->ssa_args.src1 == old &&
- !ins->ssa_args.inline_constant) {
- ins->ssa_args.src1 = new;
+ ins->ssa_args.src[i] = new;
- mir_set_swizzle(ins, 1,
- pan_compose_swizzle(mir_get_swizzle(ins, 1), swizzle));
+ mir_set_swizzle(ins, i,
+ pan_compose_swizzle(mir_get_swizzle(ins, i), swizzle));
}
}
mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
{
mir_foreach_instr_global(ctx, ins) {
- if (ins->ssa_args.dest == old)
- ins->ssa_args.dest = new;
+ mir_rewrite_index_dst_single(ins, old, new);
}
}
*/
static unsigned
-mir_mask_of_read_components_single(unsigned src, unsigned outmask)
+mir_mask_of_read_components_single(unsigned swizzle, unsigned outmask)
{
- midgard_vector_alu_src s = vector_alu_from_unsigned(src);
unsigned mask = 0;
for (unsigned c = 0; c < 4; ++c) {
if (!(outmask & (1 << c))) continue;
- unsigned comp = (s.swizzle >> (2*c)) & 3;
+ unsigned comp = (swizzle >> (2*c)) & 3;
mask |= (1 << comp);
}
return mask;
}
+static unsigned
+mir_source_count(midgard_instruction *ins)
+{
+ if (ins->type == TAG_ALU_4) {
+ /* ALU is always binary */
+ return 2;
+ } else if (ins->type == TAG_LOAD_STORE_4) {
+ bool load = !OP_IS_STORE(ins->load_store.op);
+ return (load ? 2 : 3);
+ } else if (ins->type == TAG_TEXTURE_4) {
+ /* Coords, bias.. TODO: Offsets? */
+ return 2;
+ } else {
+ unreachable("Invalid instruction type");
+ }
+}
+
+static unsigned
+mir_component_count_implicit(midgard_instruction *ins, unsigned i)
+{
+ if (ins->type == TAG_LOAD_STORE_4) {
+ switch (ins->load_store.op) {
+ /* Address implicitly 64-bit */
+ case midgard_op_ld_int4:
+ return (i == 0) ? 1 : 0;
+
+ case midgard_op_st_int4:
+ return (i == 1) ? 1 : 0;
+
+ default:
+ return 0;
+ }
+ }
+
+ return 0;
+}
+
unsigned
mir_mask_of_read_components(midgard_instruction *ins, unsigned node)
{
- assert(ins->type == TAG_ALU_4);
-
unsigned mask = 0;
- if (ins->ssa_args.src0 == node)
- mask |= mir_mask_of_read_components_single(ins->alu.src1, ins->mask);
+ for (unsigned i = 0; i < mir_source_count(ins); ++i) {
+ if (ins->ssa_args.src[i] != node) continue;
+
+ unsigned swizzle = mir_get_swizzle(ins, i);
+ unsigned m = mir_mask_of_read_components_single(swizzle, ins->mask);
+
+ /* Sometimes multi-arg ops are passed implicitly */
+ unsigned implicit = mir_component_count_implicit(ins, i);
+ assert(implicit < 2);
- if (ins->ssa_args.src1 == node && !ins->ssa_args.inline_constant)
- mask |= mir_mask_of_read_components_single(ins->alu.src2, ins->mask);
+ /* Extend the mask */
+ if (implicit == 1) {
+ /* Ensure it's a single bit currently */
+ assert((m >> __builtin_ctz(m)) == 0x1);
+
+ /* Set the next bit to extend one*/
+ m |= (m << 1);
+ }
+
+ mask |= m;
+ }
return mask;
}
+
+unsigned
+mir_ubo_shift(midgard_load_store_op op)
+{
+ switch (op) {
+ case midgard_op_ld_ubo_char:
+ return 0;
+ case midgard_op_ld_ubo_char2:
+ return 1;
+ case midgard_op_ld_ubo_char4:
+ return 2;
+ case midgard_op_ld_ubo_short4:
+ return 3;
+ case midgard_op_ld_ubo_int4:
+ return 4;
+ default:
+ unreachable("Invalid op");
+ }
+}
+
+
projects / mesa.git / blobdiff