Merge zizzer:/z/m5/Bitkeeper/newmem

[gem5.git] / src / python / m5 / objects / BaseCPU.py

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 81e09c94cac6246806a1a7dfc85f48f0ea44c379..41e90b12b9762f19fb4f2a8877c34e35f8bc9ae3 100644 (file)
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -43,6 +43,7 @@ class BaseCPU(SimObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+#        self.mem = dc
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
         self.addPrivateSplitL1Caches(ic, dc)