add boiler plate intel nic code

[gem5.git] / src / python / m5 / objects / Pci.py

diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index 29014bb37053a2032790e8f885229636b5e29699..55bf23534b744fe8952bc81be46874731aab6f63 100644 (file)
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 from Device import BasicPioDevice, DmaDevice, PioDevice
 
 class PciConfigData(SimObject):
@@ -48,12 +50,13 @@ class PciConfigAll(PioDevice):
 class PciDevice(DmaDevice):
     type = 'PciDevice'
     abstract = True
-    config = Port("PCI configuration space port")
+    config = Port(Self.pio.peerObj.port, "PCI configuration space port")
     pci_bus = Param.Int("PCI bus")
     pci_dev = Param.Int("PCI device number")
     pci_func = Param.Int("PCI function code")
-    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
     configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+    config_latency = Param.Latency('20ns', "Config read or write latency")
 
 class PciFake(PciDevice):
     type = 'PciFake'