convert SPRs and others to Data.data/ok

[soc.git] / src / scoreboard / addr_match.py

diff --git a/src/scoreboard/addr_match.py b/src/scoreboard/addr_match.py
index 6c4f6832276956a00ccf66afd11993a71aed553d..e42bbe527c1c069011819dc683e9298e19412200 100644 (file)
--- a/src/scoreboard/addr_match.py
+++ b/src/scoreboard/addr_match.py
@@ -61,7 +61,8 @@ class PartialAddrMatch(Elaboratable):
         sync = m.d.sync
 
         m.submodules.l = l = SRLatch(llen=self.n_adr, sync=False)
-        addrs_r = Array(Signal(self.bitwid, "a_r") for i in range(self.n_adr))
+        addrs_r = Array(Signal(self.bitwid, name="a_r") \
+                                for i in range(self.n_adr))
 
         # latch set/reset
         comb += l.s.eq(self.addr_en_i)
@@ -74,15 +75,15 @@ class PartialAddrMatch(Elaboratable):
         # is there a clash, yes/no
         matchgrp = []
         for i in range(self.n_adr):
-            nomatch = []
+            match = []
             for j in range(self.n_adr):
                 if i == j:
-                    nomatch.append(Const(1)) # don't match against self!
+                    match.append(Const(0)) # don't match against self!
                 else:
-                    nomatch.append(addrs_r[i] != addrs_r[j])
-            matchgrp.append((~Cat(*nomatch)).bool()) # true if all matches fail
-            comb += self.addr_nomatch_o[i].eq(Cat(*nomatch) & l.q)
-        comb += self.addr_nomatch_o.eq((~Cat(*matchgrp)) & l.q)
+                    match.append(addrs_r[i] == addrs_r[j])
+            comb += self.addr_nomatch_a_o[i].eq(~Cat(*match) & l.q)
+            matchgrp.append(self.addr_nomatch_a_o[i] == l.q)
+        comb += self.addr_nomatch_o.eq(Cat(*matchgrp) & l.q)
             
         return m