mem: Make the XBar responsible for tracking response routing

[gem5.git] / src / sim / BaseTLB.py

diff --git a/src/sim/BaseTLB.py b/src/sim/BaseTLB.py
index 9aca4a97c461e8e03f1a800a706bfaae97aa80b3..8a03413a9255f3b8d78370353c24d25807ed88b1 100644 (file)
--- a/src/sim/BaseTLB.py
+++ b/src/sim/BaseTLB.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
 class BaseTLB(SimObject):
     type = 'BaseTLB'
     abstract = True
+    cxx_header = "sim/tlb.hh"