-# Copyright (c) 2012, 2015 ARM Limited
+# Copyright (c) 2012, 2015-2016 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# parent's clock domain by default
clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain")
+ # Power model for this ClockedObject
+ power_model = VectorParam.PowerModel([], "Power models")
+
# Provide initial power state, should ideally get redefined in startup
# routine
default_p_state = Param.PwrState("UNDEFINED", "Default Power State")
- p_state_clk_gate_min = Param.Latency('1ns', "Min value of the distribution")
- p_state_clk_gate_max = Param.Latency('1s', "Max value of the distribution")
+ p_state_clk_gate_min = Param.Latency('1ns',"Min value of the distribution")
+ p_state_clk_gate_max = Param.Latency('1s',"Max value of the distribution")
p_state_clk_gate_bins = Param.Unsigned('20',
"# bins in clk gated distribution")