syscall_emul: standardized file descriptor name and add return checks.

[gem5.git] / src / sim / SConscript

diff --git a/src/sim/SConscript b/src/sim/SConscript
index 7d75a94395070711e1e2532acae8928a4e0c9c9b..0b3a35915e0fe98a68afb13364ed743975452bae 100644 (file)
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -30,7 +30,6 @@
 
 Import('*')
 
-SimObject('BaseTLB.py')
 SimObject('ClockedObject.py')
 SimObject('TickedObject.py')
 SimObject('Root.py')
@@ -43,10 +42,15 @@ SimObject('SubSystem.py')
 Source('arguments.cc')
 Source('async.cc')
 Source('core.cc')
+Source('cxx_config.cc')
+Source('cxx_manager.cc')
+Source('cxx_config_ini.cc')
 Source('debug.cc')
+Source('py_interact.cc', skip_no_python=True)
 Source('eventq.cc')
 Source('global_event.cc')
-Source('init.cc')
+Source('init.cc', skip_no_python=True)
+Source('init_signals.cc')
 Source('main.cc', main=True, skip_lib=True)
 Source('root.cc')
 Source('serialize.cc')
@@ -57,6 +61,7 @@ Source('sub_system.cc')
 Source('ticked_object.cc')
 Source('simulate.cc')
 Source('stat_control.cc')
+Source('stat_register.cc', skip_no_python=True)
 Source('clock_domain.cc')
 Source('voltage_domain.cc')
 Source('system.cc')
@@ -67,12 +72,13 @@ if env['TARGET_ISA'] != 'null':
     SimObject('Process.py')
     Source('faults.cc')
     Source('process.cc')
+    Source('fd_entry.cc')
     Source('pseudo_inst.cc')
     Source('syscall_emul.cc')
-    Source('tlb.cc')
 
 DebugFlag('Checkpoint')
 DebugFlag('Config')
+DebugFlag('CxxConfig')
 DebugFlag('Drain')
 DebugFlag('Event')
 DebugFlag('Fault')
@@ -85,7 +91,6 @@ DebugFlag('PseudoInst')
 DebugFlag('Stack')
 DebugFlag('SyscallVerbose')
 DebugFlag('TimeSync')
-DebugFlag('TLB')
 DebugFlag('Thread')
 DebugFlag('Timer')
 DebugFlag('VtoPhys')