Import('*')
-SimObject('BaseTLB.py')
SimObject('ClockedObject.py')
SimObject('TickedObject.py')
SimObject('Root.py')
SimObject('System.py')
SimObject('DVFSHandler.py')
SimObject('SubSystem.py')
+SimObject('RedirectPath.py')
Source('arguments.cc')
Source('async.cc')
+Source('backtrace_%s.cc' % env['BACKTRACE_IMPL'])
Source('core.cc')
+Source('tags.cc')
Source('cxx_config.cc')
Source('cxx_manager.cc')
Source('cxx_config_ini.cc')
Source('debug.cc')
-Source('py_interact.cc', skip_no_python=True)
+Source('py_interact.cc', add_tags='python')
Source('eventq.cc')
Source('global_event.cc')
-Source('init.cc', skip_no_python=True)
+Source('init.cc', add_tags='python')
Source('init_signals.cc')
-Source('main.cc', main=True, skip_lib=True)
+Source('main.cc', tags='main')
+Source('port.cc')
+Source('python.cc', add_tags='python')
+Source('redirect_path.cc')
Source('root.cc')
Source('serialize.cc')
Source('drain.cc')
Source('ticked_object.cc')
Source('simulate.cc')
Source('stat_control.cc')
-Source('stat_register.cc', skip_no_python=True)
+Source('stat_register.cc', add_tags='python')
Source('clock_domain.cc')
Source('voltage_domain.cc')
+Source('se_signal.cc')
+Source('linear_solver.cc')
Source('system.cc')
Source('dvfs_handler.cc')
+Source('clocked_object.cc')
+Source('mathexpr.cc')
if env['TARGET_ISA'] != 'null':
SimObject('InstTracer.py')
SimObject('Process.py')
Source('faults.cc')
Source('process.cc')
+ Source('fd_array.cc')
+ Source('fd_entry.cc')
Source('pseudo_inst.cc')
Source('syscall_emul.cc')
- Source('tlb.cc')
+ Source('syscall_desc.cc')
+
+if env['TARGET_ISA'] != 'x86':
+ Source('microcode_rom.cc')
DebugFlag('Checkpoint')
DebugFlag('Config')
DebugFlag('Loader')
DebugFlag('PseudoInst')
DebugFlag('Stack')
+DebugFlag('SyscallBase')
DebugFlag('SyscallVerbose')
DebugFlag('TimeSync')
-DebugFlag('TLB')
DebugFlag('Thread')
DebugFlag('Timer')
DebugFlag('VtoPhys')
DebugFlag('ClockDomain')
DebugFlag('VoltageDomain')
DebugFlag('DVFS')
+
+CompoundFlag('SyscallAll', [ 'SyscallBase', 'SyscallVerbose'])