ARM: Implement WFE/WFI/SEV semantics.

[gem5.git] / src / sim / SConscript

diff --git a/src/sim/SConscript b/src/sim/SConscript
index 1753b33c0879352edebb76fe28fbbfa96a8aa419..b3065374bbf7d9bf52bde5596b0dcc223d452dae 100644 (file)
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -30,31 +30,52 @@
 
 Import('*')
 
+SimObject('BaseTLB.py')
 SimObject('Root.py')
-SimObject('System.py')
 SimObject('InstTracer.py')
 
 Source('async.cc')
 Source('core.cc')
 Source('debug.cc')
 Source('eventq.cc')
-Source('faults.cc')
-Source('main.cc')
+Source('init.cc')
+Source('main.cc', main=True, skip_lib=True)
 Source('root.cc')
 Source('serialize.cc')
 Source('sim_events.cc')
 Source('sim_object.cc')
 Source('simulate.cc')
-Source('startup.cc')
 Source('stat_control.cc')
-Source('system.cc')
-Source('tlb.cc')
+
+if env['TARGET_ISA'] != 'no':
+    SimObject('System.py')
+    Source('faults.cc')
+    Source('pseudo_inst.cc')
+    Source('system.cc')
 
 if env['FULL_SYSTEM']:
     Source('arguments.cc')
-    Source('pseudo_inst.cc')
-else:
+elif env['TARGET_ISA'] != 'no':
+    Source('tlb.cc')
     SimObject('Process.py')
 
     Source('process.cc')
     Source('syscall_emul.cc')
+
+TraceFlag('Checkpoint')
+TraceFlag('Config')
+TraceFlag('Event')
+TraceFlag('Fault')
+TraceFlag('Flow')
+TraceFlag('IPI')
+TraceFlag('IPR')
+TraceFlag('Interrupt')
+TraceFlag('Loader')
+TraceFlag('Stack')
+TraceFlag('SyscallVerbose')
+TraceFlag('TimeSync')
+TraceFlag('TLB')
+TraceFlag('Thread')
+TraceFlag('Timer')
+TraceFlag('VtoPhys')
+TraceFlag('WorkItems')