MEM: Introduce the master/slave port roles in the Python classes

[gem5.git] / src / sim / System.py

diff --git a/src/sim/System.py b/src/sim/System.py
index 73124ecb9317b6bd2b0c5fe14c0d6663e1f43312..88485fcf8aa0e0c6138865ef1aaf167d5c4f0c83 100644 (file)
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -39,7 +39,7 @@ class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
 
 class System(MemObject):
     type = 'System'
-    system_port = Port("System port")
+    system_port = MasterPort("System port")
 
     @classmethod
     def export_method_cxx_predecls(cls, code):