sim, arch, base: Refactor the base remote GDB class.

[gem5.git] / src / sim / core.cc

diff --git a/src/sim/core.cc b/src/sim/core.cc
index ab75e1d9a1783de9d14f197bb53200f3a648b854..00df23ed6709a5b99ab12bfa94523e539b62a64a 100644 (file)
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -1,5 +1,7 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * Copyright (c) 2013 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,17 +31,17 @@
  *          Steve Reinhardt
  */
 
+#include "sim/core.hh"
+
 #include <iostream>
 #include <string>
 
 #include "base/callback.hh"
 #include "base/output.hh"
-#include "sim/core.hh"
+#include "sim/eventq.hh"
 
 using namespace std;
 
-Tick _curTick = 0;
-
 namespace SimClock {
 /// The simulated frequency of curTick(). (In ticks per second)
 Tick Frequency;
@@ -117,7 +119,7 @@ registerExitCallback(Callback *callback)
 }
 
 /**
- * Do C++ simulator exit processing.  Exported to SWIG to be invoked
+ * Do C++ simulator exit processing.  Exported to Python to be invoked
  * when simulator terminates via Python's atexit mechanism.
  */
 void