mem-cache: Fix setting prefetch bit

[gem5.git] / src / sim / insttracer.hh

diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 6819c2199e9fc7c898874992b4508a7a51d1e95a..22e24891032bcf15bca59b1f45a355c856480430 100644 (file)
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 ARM Limited
+ * Copyright (c) 2014, 2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -36,18 +36,15 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Nathan Binkert
  */
 
 #ifndef __INSTRECORD_HH__
 #define __INSTRECORD_HH__
 
-#include "base/bigint.hh"
-#include "base/trace.hh"
+#include "arch/generic/vec_pred_reg.hh"
+#include "arch/generic/vec_reg.hh"
 #include "base/types.hh"
-#include "cpu/inst_seq.hh"      // for InstSeqNum
+#include "cpu/inst_seq.hh"
 #include "cpu/static_inst.hh"
 #include "sim/sim_object.hh"
 
@@ -97,6 +94,9 @@ class InstRecord
     union {
         uint64_t as_int;
         double as_double;
+        ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
+        ::VecPredRegContainer<TheISA::VecPredRegSizeBits,
+                              TheISA::VecPredRegHasPackedRepr>* as_pred;
     } data;
 
     /** @defgroup fetch_seq
@@ -114,13 +114,15 @@ class InstRecord
     /** @ingroup data
      * What size of data was written?
      */
-    enum {
+    enum DataStatus {
         DataInvalid = 0,
         DataInt8 = 1,   // set to equal number of bytes
         DataInt16 = 2,
         DataInt32 = 4,
         DataInt64 = 8,
-        DataDouble = 3
+        DataDouble = 3,
+        DataVec = 5,
+        DataVecPred = 6
     } data_status;
 
     /** @ingroup memory
@@ -141,6 +143,12 @@ class InstRecord
      */
     bool predicate;
 
+    /**
+     * Did the execution of this instruction fault? (requires ExecFaulting
+     * to be enabled)
+     */
+    bool faulting;
+
   public:
     InstRecord(Tick _when, ThreadContext *_thread,
                const StaticInstPtr _staticInst,
@@ -149,10 +157,20 @@ class InstRecord
         : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
         macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
         fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
-        fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
+        fetch_seq_valid(false), cp_seq_valid(false), predicate(true),
+        faulting(false)
     { }
 
-    virtual ~InstRecord() { }
+    virtual ~InstRecord()
+    {
+        if (data_status == DataVec) {
+            assert(data.as_vec);
+            delete data.as_vec;
+        } else if (data_status == DataVecPred) {
+            assert(data.as_pred);
+            delete data.as_pred;
+        }
+    }
 
     void setWhen(Tick new_when) { when = new_when; }
     void setMem(Addr a, Addr s, unsigned f)
@@ -160,8 +178,17 @@ class InstRecord
         addr = a; size = s; flags = f; mem_valid = true;
     }
 
-    void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
-    void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
+    template <typename T, size_t N>
+    void
+    setData(std::array<T, N> d)
+    {
+        data.as_int = d[0];
+        data_status = (DataStatus)sizeof(T);
+        static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
+                      sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
+                      "Type T has an unrecognized size.");
+    }
+
     void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
     void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
     void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
@@ -174,6 +201,22 @@ class InstRecord
 
     void setData(double d) { data.as_double = d; data_status = DataDouble; }
 
+    void
+    setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d)
+    {
+        data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d);
+        data_status = DataVec;
+    }
+
+    void
+    setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits,
+                                  TheISA::VecPredRegHasPackedRepr>& d)
+    {
+        data.as_pred = new ::VecPredRegContainer<
+            TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr>(d);
+        data_status = DataVecPred;
+    }
+
     void setFetchSeq(InstSeqNum seq)
     { fetch_seq = seq; fetch_seq_valid = true; }
 
@@ -182,8 +225,10 @@ class InstRecord
 
     void setPredicate(bool val) { predicate = val; }
 
+    void setFaulting(bool val) { faulting = val; }
+
     virtual void dump() = 0;
-    
+
   public:
     Tick getWhen() const { return when; }
     ThreadContext *getThread() const { return thread; }
@@ -205,12 +250,14 @@ class InstRecord
 
     InstSeqNum getCpSeq() const { return cp_seq; }
     bool getCpSeqValid() const { return cp_seq_valid; }
+
+    bool getFaulting() const { return faulting; }
 };
 
 class InstTracer : public SimObject
 {
   public:
-    InstTracer(const Params *p) : SimObject(p)
+    InstTracer(const Params &p) : SimObject(p)
     {}
 
     virtual ~InstTracer()