kvm, x86: Adding support for SE mode execution

[gem5.git] / src / sim / insttracer.hh

diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index ebeae1fe988263ba8040c4db85620c853aa25e79..5967121200dc5b33a644d8a71590415f28d428ff 100644 (file)
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -32,10 +32,11 @@
 #ifndef __INSTRECORD_HH__
 #define __INSTRECORD_HH__
 
+#include "base/bigint.hh"
 #include "base/trace.hh"
-#include "cpu/inst_seq.hh"     // for InstSeqNum
+#include "base/types.hh"
+#include "cpu/inst_seq.hh"      // for InstSeqNum
 #include "cpu/static_inst.hh"
-#include "sim/host.hh"
 #include "sim/sim_object.hh"
 
 class ThreadContext;
@@ -53,8 +54,10 @@ class InstRecord
     // need to make this ref-counted so it doesn't go away before we
     // dump the record
     StaticInstPtr staticInst;
-    Addr PC;
+    TheISA::PCState pc;
+    StaticInstPtr macroStaticInst;
     bool misspeculating;
+    bool predicate;
 
     // The remaining fields are only valid for particular instruction
     // types (e.g, addresses for memory ops) or when particular
@@ -70,7 +73,7 @@ class InstRecord
     } data;
     enum {
         DataInvalid = 0,
-        DataInt8 = 1,  // set to equal number of bytes
+        DataInt8 = 1,   // set to equal number of bytes
         DataInt16 = 2,
         DataInt32 = 4,
         DataInt64 = 8,
@@ -85,11 +88,13 @@ class InstRecord
 
   public:
     InstRecord(Tick _when, ThreadContext *_thread,
-               const StaticInstPtr &_staticInst,
-               Addr _pc, bool spec)
+               const StaticInstPtr _staticInst,
+               TheISA::PCState _pc, bool spec,
+               const StaticInstPtr _macroStaticInst = NULL)
         : when(_when), thread(_thread),
-          staticInst(_staticInst), PC(_pc),
-          misspeculating(spec)
+          staticInst(_staticInst), pc(_pc),
+          macroStaticInst(_macroStaticInst),
+          misspeculating(spec), predicate(true)
     {
         data_status = DataInvalid;
         addr_valid = false;
@@ -100,6 +105,8 @@ class InstRecord
 
     virtual ~InstRecord() { }
 
+    void setWhen(Tick new_when) { when = new_when; }
+
     void setAddr(Addr a) { addr = a; addr_valid = true; }
 
     void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
@@ -122,13 +129,36 @@ class InstRecord
     void setCPSeq(InstSeqNum seq)
     { cp_seq = seq; cp_seq_valid = true; }
 
+    void setPredicate(bool val) { predicate = val; }
+
     virtual void dump() = 0;
+    
+  public:
+    Tick getWhen() { return when; }
+    ThreadContext *getThread() { return thread; }
+    StaticInstPtr getStaticInst() { return staticInst; }
+    TheISA::PCState getPCState() { return pc; }
+    StaticInstPtr getMacroStaticInst() { return macroStaticInst; }
+    bool getMisspeculating() { return misspeculating; }
+
+    Addr getAddr() { return addr; }
+    bool getAddrValid() { return addr_valid; }
+
+    uint64_t getIntData() { return data.as_int; }
+    double getFloatData() { return data.as_double; }
+    int getDataStatus() { return data_status; }
+
+    InstSeqNum getFetchSeq() { return fetch_seq; }
+    bool getFetchSeqValid() { return fetch_seq_valid; }
+
+    InstSeqNum getCpSeq() { return cp_seq; }
+    bool getCpSeqValid() { return cp_seq_valid; }
 };
 
 class InstTracer : public SimObject
 {
   public:
-    InstTracer(const std::string & name) : SimObject(name)
+    InstTracer(const Params *p) : SimObject(p)
     {}
 
     virtual ~InstTracer()
@@ -136,11 +166,12 @@ class InstTracer : public SimObject
 
     virtual InstRecord *
         getInstRecord(Tick when, ThreadContext *tc,
-                const StaticInstPtr staticInst, Addr pc) = 0;
+                const StaticInstPtr staticInst, TheISA::PCState pc,
+                const StaticInstPtr macroStaticInst = NULL) = 0;
 };
 
 
 
-}; // namespace Trace
+} // namespace Trace
 
 #endif // __INSTRECORD_HH__