LSQ Unit: After deleting part of a split request, set it to NULL so that it

[gem5.git] / src / sim / insttracer.hh

diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 9a20c7c565e808b6cb6afdc798cc19dc39c245c7..a8cdff671f36c61373533bd98dcedeb3d02136f9 100644 (file)
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -34,9 +34,9 @@
 
 #include "base/bigint.hh"
 #include "base/trace.hh"
-#include "cpu/inst_seq.hh"     // for InstSeqNum
+#include "base/types.hh"
+#include "cpu/inst_seq.hh"      // for InstSeqNum
 #include "cpu/static_inst.hh"
-#include "sim/host.hh"
 #include "sim/sim_object.hh"
 
 class ThreadContext;
@@ -55,6 +55,8 @@ class InstRecord
     // dump the record
     StaticInstPtr staticInst;
     Addr PC;
+    StaticInstPtr macroStaticInst;
+    MicroPC upc;
     bool misspeculating;
 
     // The remaining fields are only valid for particular instruction
@@ -71,7 +73,7 @@ class InstRecord
     } data;
     enum {
         DataInvalid = 0,
-        DataInt8 = 1,  // set to equal number of bytes
+        DataInt8 = 1,   // set to equal number of bytes
         DataInt16 = 2,
         DataInt32 = 4,
         DataInt64 = 8,
@@ -86,10 +88,13 @@ class InstRecord
 
   public:
     InstRecord(Tick _when, ThreadContext *_thread,
-               const StaticInstPtr &_staticInst,
-               Addr _pc, bool spec)
+               const StaticInstPtr _staticInst,
+               Addr _pc, bool spec,
+               const StaticInstPtr _macroStaticInst = NULL,
+               MicroPC _upc = 0)
         : when(_when), thread(_thread),
           staticInst(_staticInst), PC(_pc),
+          macroStaticInst(_macroStaticInst), upc(_upc),
           misspeculating(spec)
     {
         data_status = DataInvalid;
@@ -124,6 +129,28 @@ class InstRecord
     { cp_seq = seq; cp_seq_valid = true; }
 
     virtual void dump() = 0;
+    
+  public:
+    Tick getWhen() { return when; }
+    ThreadContext *getThread() { return thread; }
+    StaticInstPtr getStaticInst() { return staticInst; }
+    Addr getPC() { return PC; }
+    StaticInstPtr getMacroStaticInst() { return macroStaticInst; }
+    MicroPC getUPC() { return upc; } 
+    bool getMisspeculating() { return misspeculating; }
+
+    Addr getAddr() { return addr; }
+    bool getAddrValid() { return addr_valid; }
+
+    uint64_t getIntData() { return data.as_int; }
+    double getFloatData() { return data.as_double; }
+    int getDataStatus() { return data_status; }
+
+    InstSeqNum getFetchSeq() { return fetch_seq; }
+    bool getFetchSeqValid() { return fetch_seq_valid; }
+
+    InstSeqNum getCpSeq() { return cp_seq; }
+    bool getCpSeqValid() { return cp_seq_valid; }
 };
 
 class InstTracer : public SimObject
@@ -137,7 +164,9 @@ class InstTracer : public SimObject
 
     virtual InstRecord *
         getInstRecord(Tick when, ThreadContext *tc,
-                const StaticInstPtr staticInst, Addr pc) = 0;
+                const StaticInstPtr staticInst, Addr pc,
+                const StaticInstPtr macroStaticInst = NULL,
+                MicroPC _upc = 0) = 0;
 };