/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
#include <cerrno>
#include <fstream>
#include <string>
+#include <vector>
+#include "arch/kernel_stats.hh"
+#include "arch/utility.hh"
#include "arch/vtophys.hh"
+#include "arch/pseudo_inst.hh"
#include "base/debug.hh"
-#include "config/full_system.hh"
+#include "base/output.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
+#include "debug/PseudoInst.hh"
#include "debug/Quiesce.hh"
#include "debug/WorkItems.hh"
#include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
#include "sim/serialize.hh"
#include "sim/sim_events.hh"
#include "sim/stat_control.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
#include "sim/vptr.hh"
-#endif
using namespace std;
namespace PseudoInst {
-#if FULL_SYSTEM
+static inline void
+panicFsOnlyPseudoInst(const char *name)
+{
+ panic("Pseudo inst \"%s\" is only available in Full System mode.");
+}
+
+uint64_t
+pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc)
+{
+ uint64_t args[4];
+
+ DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i, %i)\n", func, subfunc);
+
+ // We need to do this in a slightly convoluted way since
+ // getArgument() might have side-effects on arg_num. We could have
+ // used the Argument class, but due to the possible side effects
+ // from getArgument, it'd most likely break.
+ int arg_num(0);
+ for (int i = 0; i < sizeof(args) / sizeof(*args); ++i) {
+ args[arg_num] = getArgument(tc, arg_num, sizeof(uint64_t), false);
+ ++arg_num;
+ }
+
+ switch (func) {
+ case 0x00: // arm_func
+ arm(tc);
+ break;
+
+ case 0x01: // quiesce_func
+ quiesce(tc);
+ break;
+
+ case 0x02: // quiescens_func
+ quiesceSkip(tc);
+ break;
+
+ case 0x03: // quiescecycle_func
+ quiesceNs(tc, args[0]);
+ break;
+
+ case 0x04: // quiescetime_func
+ return quiesceTime(tc);
+
+ case 0x07: // rpns_func
+ return rpns(tc);
+
+ case 0x09: // wakecpu_func
+ wakeCPU(tc, args[0]);
+ break;
+
+ case 0x21: // exit_func
+ m5exit(tc, args[0]);
+ break;
+
+ case 0x22:
+ m5fail(tc, args[0], args[1]);
+ break;
+
+ case 0x30: // initparam_func
+ return initParam(tc);
+
+ case 0x31: // loadsymbol_func
+ loadsymbol(tc);
+ break;
+
+ case 0x40: // resetstats_func
+ resetstats(tc, args[0], args[1]);
+ break;
+
+ case 0x41: // dumpstats_func
+ dumpstats(tc, args[0], args[1]);
+ break;
+
+ case 0x42: // dumprststats_func
+ dumpresetstats(tc, args[0], args[1]);
+ break;
+
+ case 0x43: // ckpt_func
+ m5checkpoint(tc, args[0], args[1]);
+ break;
+
+ case 0x4f: // writefile_func
+ return writefile(tc, args[0], args[1], args[2], args[3]);
+
+ case 0x50: // readfile_func
+ return readfile(tc, args[0], args[1], args[2]);
+
+ case 0x51: // debugbreak_func
+ debugbreak(tc);
+ break;
+
+ case 0x52: // switchcpu_func
+ switchcpu(tc);
+ break;
+
+ case 0x53: // addsymbol_func
+ addsymbol(tc, args[0], args[1]);
+ break;
+
+ case 0x54: // panic_func
+ panic("M5 panic instruction called at %s\n", tc->pcState());
+
+ case 0x5a: // work_begin_func
+ workbegin(tc, args[0], args[1]);
+ break;
+
+ case 0x5b: // work_end_func
+ workend(tc, args[0], args[1]);
+ break;
+
+ case 0x55: // annotate_func
+ case 0x56: // reserved2_func
+ case 0x57: // reserved3_func
+ case 0x58: // reserved4_func
+ case 0x59: // reserved5_func
+ warn("Unimplemented m5 op (0x%x)\n", func);
+ break;
+
+ /* SE mode functions */
+ case 0x60: // syscall_func
+ m5Syscall(tc);
+ break;
+
+ case 0x61: // pagefault_func
+ m5PageFault(tc);
+ break;
+
+ default:
+ warn("Unhandled m5 op: 0x%x\n", func);
+ break;
+ }
+
+ return 0;
+}
void
arm(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::arm()\n");
+ if (!FullSystem)
+ panicFsOnlyPseudoInst("arm");
+
if (tc->getKernelStats())
tc->getKernelStats()->arm();
}
void
quiesce(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::quiesce()\n");
+ if (!FullSystem)
+ panicFsOnlyPseudoInst("quiesce");
+
if (!tc->getCpuPtr()->params()->do_quiesce)
return;
void
quiesceSkip(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::quiesceSkip()\n");
+ if (!FullSystem)
+ panicFsOnlyPseudoInst("quiesceSkip");
+
BaseCPU *cpu = tc->getCpuPtr();
if (!cpu->params()->do_quiesce)
void
quiesceNs(ThreadContext *tc, uint64_t ns)
{
+ DPRINTF(PseudoInst, "PseudoInst::quiesceNs(%i)\n", ns);
+ if (!FullSystem)
+ panicFsOnlyPseudoInst("quiesceNs");
+
BaseCPU *cpu = tc->getCpuPtr();
if (!cpu->params()->do_quiesce || ns == 0)
void
quiesceCycles(ThreadContext *tc, uint64_t cycles)
{
+ DPRINTF(PseudoInst, "PseudoInst::quiesceCycles(%i)\n", cycles);
+ if (!FullSystem)
+ panicFsOnlyPseudoInst("quiesceCycles");
+
BaseCPU *cpu = tc->getCpuPtr();
if (!cpu->params()->do_quiesce || cycles == 0)
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
- Tick resume = curTick() + cpu->ticks(cycles);
+ Tick resume = cpu->clockEdge(Cycles(cycles));
cpu->reschedule(quiesceEvent, resume, true);
uint64_t
quiesceTime(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::quiesceTime()\n");
+ if (!FullSystem) {
+ panicFsOnlyPseudoInst("quiesceTime");
+ return 0;
+ }
+
return (tc->readLastActivate() - tc->readLastSuspend()) /
SimClock::Int::ns;
}
-#endif
-
uint64_t
rpns(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::rpns()\n");
return curTick() / SimClock::Int::ns;
}
void
wakeCPU(ThreadContext *tc, uint64_t cpuid)
{
+ DPRINTF(PseudoInst, "PseudoInst::wakeCPU(%i)\n", cpuid);
System *sys = tc->getSystemPtr();
ThreadContext *other_tc = sys->threadContexts[cpuid];
if (other_tc->status() == ThreadContext::Suspended)
void
m5exit(ThreadContext *tc, Tick delay)
{
+ DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay);
Tick when = curTick() + delay * SimClock::Int::ns;
- exitSimLoop("m5_exit instruction encountered", 0, when);
+ exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
}
-#if FULL_SYSTEM
+void
+m5fail(ThreadContext *tc, Tick delay, uint64_t code)
+{
+ DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code);
+ Tick when = curTick() + delay * SimClock::Int::ns;
+ exitSimLoop("m5_fail instruction encountered", code, when, 0, true);
+}
void
loadsymbol(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::loadsymbol()\n");
+ if (!FullSystem)
+ panicFsOnlyPseudoInst("loadsymbol");
+
const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
if (filename.empty()) {
return;
void
addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
{
+ DPRINTF(PseudoInst, "PseudoInst::addsymbol(0x%x, 0x%x)\n",
+ addr, symbolAddr);
+ if (!FullSystem)
+ panicFsOnlyPseudoInst("addSymbol");
+
char symb[100];
CopyStringOut(tc, symb, symbolAddr, 100);
std::string symbol(symb);
debugSymbolTable->insert(addr,symbol);
}
-#endif
+uint64_t
+initParam(ThreadContext *tc)
+{
+ DPRINTF(PseudoInst, "PseudoInst::initParam()\n");
+ if (!FullSystem) {
+ panicFsOnlyPseudoInst("initParam");
+ return 0;
+ }
+
+ return tc->getCpuPtr()->system->init_param;
+}
void
resetstats(ThreadContext *tc, Tick delay, Tick period)
{
+ DPRINTF(PseudoInst, "PseudoInst::resetstats(%i, %i)\n", delay, period);
if (!tc->getCpuPtr()->params()->do_statistics_insts)
return;
void
dumpstats(ThreadContext *tc, Tick delay, Tick period)
{
+ DPRINTF(PseudoInst, "PseudoInst::dumpstats(%i, %i)\n", delay, period);
if (!tc->getCpuPtr()->params()->do_statistics_insts)
return;
void
dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
{
+ DPRINTF(PseudoInst, "PseudoInst::dumpresetstats(%i, %i)\n", delay, period);
if (!tc->getCpuPtr()->params()->do_statistics_insts)
return;
void
m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
{
+ DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period);
if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
return;
exitSimLoop("checkpoint", 0, when, repeat);
}
-#if FULL_SYSTEM
-
uint64_t
readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
{
+ DPRINTF(PseudoInst, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n",
+ vaddr, len, offset);
+ if (!FullSystem) {
+ panicFsOnlyPseudoInst("readfile");
+ return 0;
+ }
+
const string &file = tc->getSystemPtr()->params()->readfile;
if (file.empty()) {
return ULL(0);
return result;
}
-#endif
+uint64_t
+writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset,
+ Addr filename_addr)
+{
+ DPRINTF(PseudoInst, "PseudoInst::writefile(0x%x, 0x%x, 0x%x, 0x%x)\n",
+ vaddr, len, offset, filename_addr);
+ ostream *os;
+
+ // copy out target filename
+ char fn[100];
+ std::string filename;
+ CopyStringOut(tc, fn, filename_addr, 100);
+ filename = std::string(fn);
+
+ if (offset == 0) {
+ // create a new file (truncate)
+ os = simout.create(filename, true);
+ } else {
+ // do not truncate file if offset is non-zero
+ // (ios::in flag is required as well to keep the existing data
+ // intact, otherwise existing data will be zeroed out.)
+ os = simout.openFile(simout.directory() + filename,
+ ios::in | ios::out | ios::binary);
+ }
+ if (!os)
+ panic("could not open file %s\n", filename);
+
+ // seek to offset
+ os->seekp(offset);
+
+ // copy out data and write to file
+ char *buf = new char[len];
+ CopyOut(tc, buf, vaddr, len);
+ os->write(buf, len);
+ if (os->fail() || os->bad())
+ panic("Error while doing writefile!\n");
+
+ simout.close(os);
+
+ delete [] buf;
+
+ return len;
+}
void
debugbreak(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::debugbreak()\n");
Debug::breakpoint();
}
void
switchcpu(ThreadContext *tc)
{
+ DPRINTF(PseudoInst, "PseudoInst::switchcpu()\n");
exitSimLoop("switchcpu");
}
void
workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid)
{
+ DPRINTF(PseudoInst, "PseudoInst::workbegin(%i, %i)\n", workid, threadid);
tc->getCpuPtr()->workItemBegin();
System *sys = tc->getSystemPtr();
+ const System::Params *params = sys->params();
+ sys->workItemBegin(threadid, workid);
DPRINTF(WorkItems, "Work Begin workid: %d, threadid %d\n", workid,
threadid);
// If specified, determine if this is the specific work item the user
// identified
//
- if (sys->params()->work_item_id == -1 ||
- sys->params()->work_item_id == workid) {
+ if (params->work_item_id == -1 || params->work_item_id == workid) {
uint64_t systemWorkBeginCount = sys->incWorkItemsBegin();
int cpuId = tc->getCpuPtr()->cpuId();
- if (sys->params()->work_cpus_ckpt_count != 0 &&
- sys->markWorkItem(cpuId) >= sys->params()->work_cpus_ckpt_count) {
+ if (params->work_cpus_ckpt_count != 0 &&
+ sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
//
// If active cpus equals checkpoint count, create checkpoint
//
- Event *event = new SimLoopExitEvent("checkpoint", 0);
- mainEventQueue.schedule(event, curTick());
+ exitSimLoop("checkpoint");
}
- if (systemWorkBeginCount == sys->params()->work_begin_ckpt_count) {
+ if (systemWorkBeginCount == params->work_begin_ckpt_count) {
//
// Note: the string specified as the cause of the exit event must
// exactly equal "checkpoint" inorder to create a checkpoint
//
- Event *event = new SimLoopExitEvent("checkpoint", 0);
- mainEventQueue.schedule(event, curTick());
+ exitSimLoop("checkpoint");
}
- if (systemWorkBeginCount == sys->params()->work_begin_exit_count) {
+ if (systemWorkBeginCount == params->work_begin_exit_count) {
//
// If a certain number of work items started, exit simulation
//
- Event *event = new SimLoopExitEvent("work started count reach", 0);
- mainEventQueue.schedule(event, curTick());
+ exitSimLoop("work started count reach");
}
- if (tc->getCpuPtr()->cpuId() == sys->params()->work_begin_cpu_id_exit) {
+ if (cpuId == params->work_begin_cpu_id_exit) {
//
- // If work started on the specific cpu id specified, exit simulation
+ // If work started on the cpu id specified, exit simulation
//
- Event *event = new SimLoopExitEvent("work started on specific cpu",
- 0);
-
- mainEventQueue.schedule(event, curTick() + 1);
+ exitSimLoop("work started on specific cpu");
}
}
}
void
workend(ThreadContext *tc, uint64_t workid, uint64_t threadid)
{
+ DPRINTF(PseudoInst, "PseudoInst::workend(%i, %i)\n", workid, threadid);
tc->getCpuPtr()->workItemEnd();
System *sys = tc->getSystemPtr();
+ const System::Params *params = sys->params();
+ sys->workItemEnd(threadid, workid);
DPRINTF(WorkItems, "Work End workid: %d, threadid %d\n", workid, threadid);
// If specified, determine if this is the specific work item the user
// identified
//
- if (sys->params()->work_item_id == -1 ||
- sys->params()->work_item_id == workid) {
+ if (params->work_item_id == -1 || params->work_item_id == workid) {
uint64_t systemWorkEndCount = sys->incWorkItemsEnd();
int cpuId = tc->getCpuPtr()->cpuId();
- if (sys->params()->work_cpus_ckpt_count != 0 &&
- sys->markWorkItem(cpuId) >= sys->params()->work_cpus_ckpt_count) {
+ if (params->work_cpus_ckpt_count != 0 &&
+ sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
//
// If active cpus equals checkpoint count, create checkpoint
//
- Event *event = new SimLoopExitEvent("checkpoint", 0);
- mainEventQueue.schedule(event, curTick());
+ exitSimLoop("checkpoint");
}
- if (sys->params()->work_end_ckpt_count != 0 &&
- systemWorkEndCount == sys->params()->work_end_ckpt_count) {
+ if (params->work_end_ckpt_count != 0 &&
+ systemWorkEndCount == params->work_end_ckpt_count) {
//
// If total work items completed equals checkpoint count, create
// checkpoint
//
- Event *event = new SimLoopExitEvent("checkpoint", 0);
- mainEventQueue.schedule(event, curTick());
+ exitSimLoop("checkpoint");
}
- if (sys->params()->work_end_exit_count != 0 &&
- systemWorkEndCount == sys->params()->work_end_exit_count) {
+ if (params->work_end_exit_count != 0 &&
+ systemWorkEndCount == params->work_end_exit_count) {
//
// If total work items completed equals exit count, exit simulation
//
- Event *event = new SimLoopExitEvent("work items exit count reached",
- 0);
-
- mainEventQueue.schedule(event, curTick());
+ exitSimLoop("work items exit count reached");
}
}
}
projects / gem5.git / blobdiff