cpu: implements vector registers

[gem5.git] / src / sim / pseudo_inst.cc

diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index f4666a0cd3366d484cd8bf6f8a9d469b623be759..80737003c4e6de7e25cdd763d81c1f69651741aa 100644 (file)
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -52,6 +52,7 @@
 #include "arch/kernel_stats.hh"
 #include "arch/utility.hh"
 #include "arch/vtophys.hh"
+#include "arch/pseudo_inst.hh"
 #include "base/debug.hh"
 #include "base/output.hh"
 #include "config/the_isa.hh"
@@ -64,6 +65,7 @@
 #include "debug/WorkItems.hh"
 #include "params/BaseCPU.hh"
 #include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/pseudo_inst.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_events.hh"
@@ -198,6 +200,15 @@ pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc)
         warn("Unimplemented m5 op (0x%x)\n", func);
         break;
 
+      /* SE mode functions */
+      case 0x60: // syscall_func
+        m5Syscall(tc);
+        break;
+
+      case 0x61: // pagefault_func
+        m5PageFault(tc);
+        break;
+
       default:
         warn("Unhandled m5 op: 0x%x\n", func);
         break;
@@ -347,7 +358,7 @@ m5exit(ThreadContext *tc, Tick delay)
 {
     DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay);
     Tick when = curTick() + delay * SimClock::Int::ns;
-    exitSimLoop("m5_exit instruction encountered", 0, when);
+    exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
 }
 
 void
@@ -355,7 +366,7 @@ m5fail(ThreadContext *tc, Tick delay, uint64_t code)
 {
     DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code);
     Tick when = curTick() + delay * SimClock::Int::ns;
-    exitSimLoop("m5_fail instruction encountered", code, when);
+    exitSimLoop("m5_fail instruction encountered", code, when, 0, true);
 }
 
 void