syscall_emul: standardized file descriptor name and add return checks.

[gem5.git] / src / sim / pseudo_inst.hh

diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 30996fc3bfabff4555749aacc13f3dcb3225680c..b6e32847a9e0df59f9e6cd3f277cd434d2e37197 100644 (file)
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -28,40 +40,55 @@
  * Authors: Nathan Binkert
  */
 
+#ifndef __SIM_PSEUDO_INST_HH__
+#define __SIM_PSEUDO_INST_HH__
+
 class ThreadContext;
 
 //We need the "Tick" and "Addr" data types from here
-#include "sim/host.hh"
+#include "base/types.hh"
 
 namespace PseudoInst {
 
 /**
- * @todo these externs are only here for a hack in fullCPU::takeOver...
+ * Execute a decoded M5 pseudo instruction
+ *
+ * The ISA-specific code is responsible to decode the pseudo inst
+ * function number and subfunction number. After that has been done,
+ * the rest of the instruction can be implemented in an ISA-agnostic
+ * manner using the ISA-specific getArguments functions.
+ *
+ * @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
+ * @param subfunc M5 minor function number. Mainly used for annotations.
  */
-extern bool doStatisticsInsts;
-extern bool doCheckpointInsts;
-extern bool doQuiesce;
+uint64_t pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc);
 
-#if FULL_SYSTEM
 void arm(ThreadContext *tc);
 void quiesce(ThreadContext *tc);
+void quiesceSkip(ThreadContext *tc);
 void quiesceNs(ThreadContext *tc, uint64_t ns);
 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
 uint64_t quiesceTime(ThreadContext *tc);
 uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
     uint64_t offset);
+uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
+    uint64_t offset, Addr filenameAddr);
 void loadsymbol(ThreadContext *xc);
 void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
-#endif
-
+uint64_t initParam(ThreadContext *xc);
 uint64_t rpns(ThreadContext *tc);
 void wakeCPU(ThreadContext *tc, uint64_t cpuid);
 void m5exit(ThreadContext *tc, Tick delay);
+void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
 void resetstats(ThreadContext *tc, Tick delay, Tick period);
 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
 void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
 void debugbreak(ThreadContext *tc);
 void switchcpu(ThreadContext *tc);
+void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
+void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
+
+} // namespace PseudoInst
 
-/* namespace PseudoInst */ }
+#endif // __SIM_PSEUDO_INST_HH__