cpu: implements vector registers

[gem5.git] / src / sim / sim_events.cc

diff --git a/src/sim/sim_events.cc b/src/sim/sim_events.cc
index 719a732ab4c430b3bc5141c53a2748357868ce15..94bd06191dd4eff1a871ff375423e472a0fe854d 100644 (file)
--- a/src/sim/sim_events.cc
+++ b/src/sim/sim_events.cc
@@ -137,16 +137,6 @@ LocalSimLoopExitEvent::unserialize(CheckpointIn &cp)
     UNSERIALIZE_SCALAR(repeat);
 }
 
-void
-LocalSimLoopExitEvent::unserializeEvent(CheckpointIn &cp, EventQueue *eventq)
-{
-    Event::unserializeEvent(cp, eventq);
-
-    UNSERIALIZE_SCALAR(cause);
-    UNSERIALIZE_SCALAR(code);
-    UNSERIALIZE_SCALAR(repeat);
-}
-
 Serializable *
 LocalSimLoopExitEvent::createForUnserialize(CheckpointIn &cp,
                                             const string &section)