cpu: implements vector registers

[gem5.git] / src / sim / sim_object.cc

diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index a7be4ebd2cdfe3bc04d9a57fc990a127b7485d8e..e87b7240fd7d1c2cfddaa95767183bd817c11a6c 100644 (file)
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -81,11 +81,13 @@ SimObject::init()
 }
 
 void
-SimObject::loadState(Checkpoint *cp)
+SimObject::loadState(CheckpointIn &cp)
 {
-    if (cp->sectionExists(name())) {
+    if (cp.sectionExists(name())) {
         DPRINTF(Checkpoint, "unserializing\n");
-        unserialize(cp, name());
+        // This works despite name() returning a fully qualified name
+        // since we are at the top level.
+        unserializeSection(cp, name());
     } else {
         DPRINTF(Checkpoint, "no checkpoint section found\n");
     }
@@ -140,15 +142,16 @@ SimObject::getProbeManager()
 // static function: serialize all SimObjects.
 //
 void
-SimObject::serializeAll(std::ostream &os)
+SimObject::serializeAll(CheckpointOut &cp)
 {
     SimObjectList::reverse_iterator ri = simObjectList.rbegin();
     SimObjectList::reverse_iterator rend = simObjectList.rend();
 
     for (; ri != rend; ++ri) {
         SimObject *obj = *ri;
-        obj->nameOut(os);
-        obj->serialize(os);
+        // This works despite name() returning a fully qualified name
+        // since we are at the top level.
+        obj->serializeSectionOld(cp, obj->name());
    }
 }
 
@@ -177,14 +180,6 @@ debugObjectBreak(const char *objs)
 }
 #endif
 
-unsigned int
-SimObject::drain(DrainManager *drain_manager)
-{
-    setDrainState(Drained);
-    return 0;
-}
-
-
 SimObject *
 SimObject::find(const char *name)
 {