arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher

[gem5.git] / src / sim / stat_control.cc

diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 83089f399e0a66547ad0ca8116dcfcfde80d3134..6324b36ef9e56f54326c063cc538abd731523240 100644 (file)
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -46,6 +46,8 @@
 // This file will contain default statistics for the simulator that
 // don't really belong to a specific simulator object
 
+#include "sim/stat_control.hh"
+
 #include <fstream>
 #include <iostream>
 #include <list>
@@ -56,7 +58,6 @@
 #include "base/time.hh"
 #include "cpu/base.hh"
 #include "sim/global_event.hh"
-#include "sim/stat_control.hh"
 
 using namespace std;
 
@@ -157,8 +158,8 @@ Global::Global()
     finalTick
         .functor(statFinalTick)
         .name("final_tick")
-        .desc("Number of ticks from beginning of simulation \
-(restored from checkpoints and never reset)")
+        .desc("Number of ticks from beginning of simulation "
+              "(restored from checkpoints and never reset)")
         ;
 
     hostInstRate