/*
+ * Copyright (c) 2011-2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* Copyright (c) 2011 Regents of the University of California
* All rights reserved.
* Rick Strong
*/
-#include "arch/isa_traits.hh"
#include "arch/remote_gdb.hh"
#include "arch/utility.hh"
-#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
+#include "base/str.hh"
#include "base/trace.hh"
-#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
-#include "kern/kernel_stats.hh"
-#include "mem/mem_object.hh"
+#include "debug/WorkItems.hh"
+#include "mem/abstract_mem.hh"
#include "mem/physical.hh"
-#include "mem/vport.hh"
#include "params/System.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
+/**
+ * To avoid linking errors with LTO, only include the header if we
+ * actually have a definition.
+ */
+#if THE_ISA != NULL_ISA
+#include "kern/kernel_stats.hh"
+#endif
+
using namespace std;
using namespace TheISA;
int System::numSystemsRunning = 0;
System::System(Params *p)
- : SimObject(p), physmem(p->physmem), _numContexts(0), pagePtr(0),
+ : MemObject(p), _systemPort("system_port", this),
+ _numContexts(0),
+ pagePtr(0),
init_param(p->init_param),
+ physProxy(_systemPort, p->cache_line_size),
+ kernelSymtab(nullptr),
+ kernel(nullptr),
loadAddrMask(p->load_addr_mask),
+ loadAddrOffset(p->load_offset),
nextPID(0),
+ physmem(name() + ".physmem", p->memories),
memoryMode(p->mem_mode),
+ _cacheLineSize(p->cache_line_size),
workItemsBegin(0),
workItemsEnd(0),
+ numWorkIds(p->num_work_ids),
_params(p),
- totalNumInsts(0),
+ totalNumInsts(0),
instEventQueue("system instruction-based event queue")
{
// add self to global system list
systemList.push_back(this);
- /** Keep track of all memories we can execute code out of
- * in our system
- */
- for (int x = 0; x < p->memories.size(); x++) {
- if (!p->memories[x])
- continue;
- memRanges.push_back(RangeSize(p->memories[x]->start(),
- p->memories[x]->size()));
- }
-
if (FullSystem) {
kernelSymtab = new SymbolTable;
if (!debugSymbolTable)
debugSymbolTable = new SymbolTable;
+ }
+ // check if the cache line size is a value known to work
+ if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
+ _cacheLineSize == 64 || _cacheLineSize == 128))
+ warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
- /**
- * Get a functional port to memory
- */
- Port *mem_port;
- functionalPort = new FunctionalPort(name() + "-fport");
- mem_port = physmem->getPort("functional");
- functionalPort->setPeer(mem_port);
- mem_port->setPeer(functionalPort);
-
- virtPort = new VirtualPort(name() + "-fport");
- mem_port = physmem->getPort("functional");
- virtPort->setPeer(mem_port);
- mem_port->setPeer(virtPort);
-
+ // Get the generic system master IDs
+ MasterID tmp_id M5_VAR_USED;
+ tmp_id = getMasterId("writebacks");
+ assert(tmp_id == Request::wbMasterId);
+ tmp_id = getMasterId("functional");
+ assert(tmp_id == Request::funcMasterId);
+ tmp_id = getMasterId("interrupt");
+ assert(tmp_id == Request::intMasterId);
- /**
- * Load the kernel code into memory
- */
+ if (FullSystem) {
if (params()->kernel == "") {
inform("No kernel set for full system simulation. "
- "Assuming you know what you're doing...\n");
+ "Assuming you know what you're doing\n");
} else {
- // Load kernel code
+ // Get the kernel code
kernel = createObjectFile(params()->kernel);
inform("kernel located at: %s", params()->kernel);
if (kernel == NULL)
fatal("Could not load kernel file %s", params()->kernel);
- // Load program sections into memory
- kernel->loadSections(functionalPort, loadAddrMask);
-
// setup entry points
kernelStart = kernel->textBase();
kernelEnd = kernel->bssBase() + kernel->bssSize();
if (!kernel->loadLocalSymbols(debugSymbolTable))
fatal("could not load kernel local symbols\n");
- DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
- DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd);
- DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
- DPRINTF(Loader, "Kernel loaded...\n");
+ // Loading only needs to happen once and after memory system is
+ // connected so it will happen in initState()
}
}
// increment the number of running systms
numSystemsRunning++;
- activeCpus.clear();
+ // Set back pointers to the system in all memories
+ for (int x = 0; x < params()->memories.size(); x++)
+ params()->memories[x]->system(this);
}
System::~System()
{
delete kernelSymtab;
delete kernel;
+
+ for (uint32_t j = 0; j < numWorkIds; j++)
+ delete workItemStats[j];
+}
+
+void
+System::init()
+{
+ // check that the system port is connected
+ if (!_systemPort.isConnected())
+ panic("System port on %s is not connected.\n", name());
+}
+
+BaseMasterPort&
+System::getMasterPort(const std::string &if_name, PortID idx)
+{
+ // no need to distinguish at the moment (besides checking)
+ return _systemPort;
}
void
System::setMemoryMode(Enums::MemoryMode mode)
{
- assert(getState() == Drained);
+ assert(getDrainState() == Drainable::Drained);
memoryMode = mode;
}
threadContexts[id] = tc;
_numContexts++;
+#if THE_ISA != NULL_ISA
int port = getRemoteGDBPort();
if (port) {
RemoteGDB *rgdb = new RemoteGDB(this, tc);
remoteGDB[id] = rgdb;
}
+#endif
activeCpus.push_back(false);
System::initState()
{
if (FullSystem) {
- int i;
- for (i = 0; i < threadContexts.size(); i++)
+ for (int i = 0; i < threadContexts.size(); i++)
TheISA::startupCPU(threadContexts[i], i);
+ // Moved from the constructor to here since it relies on the
+ // address map being resolved in the interconnect
+ /**
+ * Load the kernel code into memory
+ */
+ if (params()->kernel != "") {
+ if (params()->kernel_addr_check) {
+ // Validate kernel mapping before loading binary
+ if (!(isMemAddr((kernelStart & loadAddrMask) +
+ loadAddrOffset) &&
+ isMemAddr((kernelEnd & loadAddrMask) +
+ loadAddrOffset))) {
+ fatal("Kernel is mapped to invalid location (not memory). "
+ "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
+ kernelStart,
+ kernelEnd, (kernelStart & loadAddrMask) +
+ loadAddrOffset,
+ (kernelEnd & loadAddrMask) + loadAddrOffset);
+ }
+ }
+ // Load program sections into memory
+ kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset);
+
+ DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
+ DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd);
+ DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
+ DPRINTF(Loader, "Kernel loaded...\n");
+ }
}
+
+ activeCpus.clear();
}
void
}
Addr
-System::new_page()
+System::allocPhysPages(int npages)
{
- Addr return_addr = pagePtr << LogVMPageSize;
- ++pagePtr;
- if (return_addr >= physmem->size())
+ Addr return_addr = pagePtr << PageShift;
+ pagePtr += npages;
+
+ Addr next_return_addr = pagePtr << PageShift;
+
+ AddrRange m5opRange(0xffff0000, 0xffffffff);
+ if (m5opRange.contains(next_return_addr)) {
+ warn("Reached m5ops MMIO region\n");
+ return_addr = 0xffffffff;
+ pagePtr = 0xffffffff >> PageShift;
+ }
+
+ if ((pagePtr << PageShift) > physmem.totalSize())
fatal("Out of memory, please increase size of physical memory.");
return return_addr;
}
Addr
-System::memSize()
+System::memSize() const
{
- return physmem->size();
+ return physmem.totalSize();
}
Addr
-System::freeMemSize()
+System::freeMemSize() const
{
- return physmem->size() - (pagePtr << LogVMPageSize);
+ return physmem.totalSize() - (pagePtr << PageShift);
}
bool
-System::isMemory(const Addr addr) const
+System::isMemAddr(Addr addr) const
{
- std::list<Range<Addr> >::const_iterator i;
- for (i = memRanges.begin(); i != memRanges.end(); i++) {
- if (*i == addr)
- return true;
- }
- return false;
+ return physmem.isMemAddr(addr);
+}
+
+unsigned int
+System::drain(DrainManager *dm)
+{
+ setDrainState(Drainable::Drained);
+ return 0;
}
void
-System::resume()
+System::drainResume()
{
- SimObject::resume();
+ Drainable::drainResume();
totalNumInsts = 0;
}
kernelSymtab->serialize("kernel_symtab", os);
SERIALIZE_SCALAR(pagePtr);
SERIALIZE_SCALAR(nextPID);
+ serializeSymtab(os);
+
+ // also serialize the memories in the system
+ nameOut(os, csprintf("%s.physmem", name()));
+ physmem.serialize(os);
}
kernelSymtab->unserialize("kernel_symtab", cp, section);
UNSERIALIZE_SCALAR(pagePtr);
UNSERIALIZE_SCALAR(nextPID);
+ unserializeSymtab(cp, section);
+
+ // also unserialize the memories in the system
+ physmem.unserialize(cp, csprintf("%s.physmem", name()));
+}
+
+void
+System::regStats()
+{
+ for (uint32_t j = 0; j < numWorkIds ; j++) {
+ workItemStats[j] = new Stats::Histogram();
+ stringstream namestr;
+ ccprintf(namestr, "work_item_type%d", j);
+ workItemStats[j]->init(20)
+ .name(name() + "." + namestr.str())
+ .desc("Run time stat for" + namestr.str())
+ .prereq(*workItemStats[j]);
+ }
+}
+
+void
+System::workItemEnd(uint32_t tid, uint32_t workid)
+{
+ std::pair<uint32_t,uint32_t> p(tid, workid);
+ if (!lastWorkItemStarted.count(p))
+ return;
+
+ Tick samp = curTick() - lastWorkItemStarted[p];
+ DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
+
+ if (workid >= numWorkIds)
+ fatal("Got workid greater than specified in system configuration\n");
+
+ workItemStats[workid]->sample(samp);
+ lastWorkItemStarted.erase(p);
}
void
System::printSystems()
{
+ ios::fmtflags flags(cerr.flags());
+
vector<System *>::iterator i = systemList.begin();
vector<System *>::iterator end = systemList.end();
for (; i != end; ++i) {
System *sys = *i;
cerr << "System " << sys->name() << ": " << hex << sys << endl;
}
+
+ cerr.flags(flags);
}
void
System::printSystems();
}
-const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
- "timing"};
+MasterID
+System::getMasterId(std::string master_name)
+{
+ // strip off system name if the string starts with it
+ if (startswith(master_name, name()))
+ master_name = master_name.erase(0, name().size() + 1);
+
+ // CPUs in switch_cpus ask for ids again after switching
+ for (int i = 0; i < masterIds.size(); i++) {
+ if (masterIds[i] == master_name) {
+ return i;
+ }
+ }
+
+ // Verify that the statistics haven't been enabled yet
+ // Otherwise objects will have sized their stat buckets and
+ // they will be too small
+
+ if (Stats::enabled()) {
+ fatal("Can't request a masterId after regStats(). "
+ "You must do so in init().\n");
+ }
+
+ masterIds.push_back(master_name);
+
+ return masterIds.size() - 1;
+}
+
+std::string
+System::getMasterName(MasterID master_id)
+{
+ if (master_id >= masterIds.size())
+ fatal("Invalid master_id passed to getMasterName()\n");
+
+ return masterIds[master_id];
+}
System *
SystemParams::create()
projects / gem5.git / blobdiff