/*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2014 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* Rick Strong
*/
-#include "arch/isa_traits.hh"
#include "arch/remote_gdb.hh"
#include "arch/utility.hh"
-#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
+#include "base/str.hh"
#include "base/trace.hh"
-#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "debug/WorkItems.hh"
-#include "kern/kernel_stats.hh"
+#include "mem/abstract_mem.hh"
#include "mem/physical.hh"
#include "params/System.hh"
#include "sim/byteswap.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
+/**
+ * To avoid linking errors with LTO, only include the header if we
+ * actually have a definition.
+ */
+#if THE_ISA != NULL_ISA
+#include "kern/kernel_stats.hh"
+#endif
+
using namespace std;
using namespace TheISA;
_numContexts(0),
pagePtr(0),
init_param(p->init_param),
- physProxy(_systemPort),
- virtProxy(_systemPort),
+ physProxy(_systemPort, p->cache_line_size),
+ kernelSymtab(nullptr),
+ kernel(nullptr),
loadAddrMask(p->load_addr_mask),
+ loadAddrOffset(p->load_offset),
nextPID(0),
- physmem(p->memories),
+ physmem(name() + ".physmem", p->memories),
memoryMode(p->mem_mode),
+ _cacheLineSize(p->cache_line_size),
workItemsBegin(0),
workItemsEnd(0),
numWorkIds(p->num_work_ids),
debugSymbolTable = new SymbolTable;
}
+ // check if the cache line size is a value known to work
+ if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
+ _cacheLineSize == 64 || _cacheLineSize == 128))
+ warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
+
// Get the generic system master IDs
MasterID tmp_id M5_VAR_USED;
tmp_id = getMasterId("writebacks");
if (FullSystem) {
if (params()->kernel == "") {
inform("No kernel set for full system simulation. "
- "Assuming you know what you're doing if not SPARC ISA\n");
+ "Assuming you know what you're doing\n");
} else {
// Get the kernel code
kernel = createObjectFile(params()->kernel);
panic("System port on %s is not connected.\n", name());
}
-MasterPort&
-System::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort&
+System::getMasterPort(const std::string &if_name, PortID idx)
{
// no need to distinguish at the moment (besides checking)
return _systemPort;
void
System::setMemoryMode(Enums::MemoryMode mode)
{
- assert(getState() == Drained);
+ assert(getDrainState() == Drainable::Drained);
memoryMode = mode;
}
threadContexts[id] = tc;
_numContexts++;
+#if THE_ISA != NULL_ISA
int port = getRemoteGDBPort();
if (port) {
RemoteGDB *rgdb = new RemoteGDB(this, tc);
remoteGDB[id] = rgdb;
}
+#endif
activeCpus.push_back(false);
void
System::initState()
{
- int i;
if (FullSystem) {
- for (i = 0; i < threadContexts.size(); i++)
+ for (int i = 0; i < threadContexts.size(); i++)
TheISA::startupCPU(threadContexts[i], i);
// Moved from the constructor to here since it relies on the
// address map being resolved in the interconnect
* Load the kernel code into memory
*/
if (params()->kernel != "") {
+ if (params()->kernel_addr_check) {
+ // Validate kernel mapping before loading binary
+ if (!(isMemAddr((kernelStart & loadAddrMask) +
+ loadAddrOffset) &&
+ isMemAddr((kernelEnd & loadAddrMask) +
+ loadAddrOffset))) {
+ fatal("Kernel is mapped to invalid location (not memory). "
+ "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
+ kernelStart,
+ kernelEnd, (kernelStart & loadAddrMask) +
+ loadAddrOffset,
+ (kernelEnd & loadAddrMask) + loadAddrOffset);
+ }
+ }
// Load program sections into memory
- kernel->loadSections(physProxy, loadAddrMask);
+ kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset);
DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd);
}
activeCpus.clear();
-
- if (!FullSystem)
- return;
-
- for (i = 0; i < threadContexts.size(); i++)
- TheISA::startupCPU(threadContexts[i], i);
}
void
Addr
System::allocPhysPages(int npages)
{
- Addr return_addr = pagePtr << LogVMPageSize;
+ Addr return_addr = pagePtr << PageShift;
pagePtr += npages;
- if ((pagePtr << LogVMPageSize) > physmem.totalSize())
+
+ Addr next_return_addr = pagePtr << PageShift;
+
+ AddrRange m5opRange(0xffff0000, 0xffffffff);
+ if (m5opRange.contains(next_return_addr)) {
+ warn("Reached m5ops MMIO region\n");
+ return_addr = 0xffffffff;
+ pagePtr = 0xffffffff >> PageShift;
+ }
+
+ if ((pagePtr << PageShift) > physmem.totalSize())
fatal("Out of memory, please increase size of physical memory.");
return return_addr;
}
Addr
System::freeMemSize() const
{
- return physmem.totalSize() - (pagePtr << LogVMPageSize);
+ return physmem.totalSize() - (pagePtr << PageShift);
}
bool
return physmem.isMemAddr(addr);
}
+unsigned int
+System::drain(DrainManager *dm)
+{
+ setDrainState(Drainable::Drained);
+ return 0;
+}
+
void
-System::resume()
+System::drainResume()
{
- SimObject::resume();
+ Drainable::drainResume();
totalNumInsts = 0;
}
kernelSymtab->serialize("kernel_symtab", os);
SERIALIZE_SCALAR(pagePtr);
SERIALIZE_SCALAR(nextPID);
+ serializeSymtab(os);
+
+ // also serialize the memories in the system
+ nameOut(os, csprintf("%s.physmem", name()));
+ physmem.serialize(os);
}
kernelSymtab->unserialize("kernel_symtab", cp, section);
UNSERIALIZE_SCALAR(pagePtr);
UNSERIALIZE_SCALAR(nextPID);
+ unserializeSymtab(cp, section);
+
+ // also unserialize the memories in the system
+ physmem.unserialize(cp, csprintf("%s.physmem", name()));
}
void
void
System::printSystems()
{
+ ios::fmtflags flags(cerr.flags());
+
vector<System *>::iterator i = systemList.begin();
vector<System *>::iterator end = systemList.end();
for (; i != end; ++i) {
System *sys = *i;
cerr << "System " << sys->name() << ": " << hex << sys << endl;
}
+
+ cerr.flags(flags);
}
void
System::getMasterId(std::string master_name)
{
// strip off system name if the string starts with it
- if (master_name.size() > name().size() &&
- master_name.compare(0, name().size(), name()) == 0)
+ if (startswith(master_name, name()))
master_name = master_name.erase(0, name().size() + 1);
// CPUs in switch_cpus ask for ids again after switching
// Otherwise objects will have sized their stat buckets and
// they will be too small
- if (Stats::enabled())
- fatal("Can't request a masterId after regStats(). \
- You must do so in init().\n");
+ if (Stats::enabled()) {
+ fatal("Can't request a masterId after regStats(). "
+ "You must do so in init().\n");
+ }
masterIds.push_back(master_name);
return masterIds[master_id];
}
-const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
- "timing"};
-
System *
SystemParams::create()
{
projects / gem5.git / blobdiff