/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* Copyright (c) 2011 Regents of the University of California
* All rights reserved.
#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
#include "kern/system_events.hh"
+#include "mem/fs_translating_port_proxy.hh"
+#include "mem/mem_object.hh"
#include "mem/port.hh"
+#include "mem/physical.hh"
#include "params/System.hh"
-#include "sim/sim_object.hh"
class BaseCPU;
class BaseRemoteGDB;
-class FunctionalPort;
class GDBListener;
class ObjectFile;
-class PhysicalMemory;
class Platform;
class ThreadContext;
-class VirtualPort;
-class System : public SimObject
+class System : public MemObject
{
+ private:
+
+ /**
+ * Private class for the system port which is only used as a
+ * master for debug access and for non-structural entities that do
+ * not have a port of their own.
+ */
+ class SystemPort : public MasterPort
+ {
+ public:
+
+ /**
+ * Create a system port with a name and an owner.
+ */
+ SystemPort(const std::string &_name, MemObject *_owner)
+ : MasterPort(_name, _owner)
+ { }
+ bool recvTimingResp(PacketPtr pkt)
+ { panic("SystemPort does not receive timing!\n"); return false; }
+ void recvRetry()
+ { panic("SystemPort does not expect retry!\n"); }
+ };
+
+ SystemPort _systemPort;
+
public:
- static const char *MemoryModeStrings[3];
+ /**
+ * After all objects have been created and all ports are
+ * connected, check that the system port is connected.
+ */
+ virtual void init();
- Enums::MemoryMode
- getMemoryMode()
- {
- assert(memoryMode);
- return memoryMode;
+ /**
+ * Get a reference to the system port that can be used by
+ * non-structural simulation objects like processes or threads, or
+ * external entities like loaders and debuggers, etc, to access
+ * the memory system.
+ *
+ * @return a reference to the system port we own
+ */
+ MasterPort& getSystemPort() { return _systemPort; }
+
+ /**
+ * Additional function to return the Port of a memory object.
+ */
+ BaseMasterPort& getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
+
+ static const char *MemoryModeStrings[4];
+
+ /** @{ */
+ /**
+ * Is the system in atomic mode?
+ *
+ * There are currently two different atomic memory modes:
+ * 'atomic', which supports caches; and 'atomic_noncaching', which
+ * bypasses caches. The latter is used by hardware virtualized
+ * CPUs. SimObjects are expected to use Port::sendAtomic() and
+ * Port::recvAtomic() when accessing memory in this mode.
+ */
+ bool isAtomicMode() const {
+ return memoryMode == Enums::atomic ||
+ memoryMode == Enums::atomic_noncaching;
+ }
+
+ /**
+ * Is the system in timing mode?
+ *
+ * SimObjects are expected to use Port::sendTiming() and
+ * Port::recvTiming() when accessing memory in this mode.
+ */
+ bool isTimingMode() const {
+ return memoryMode == Enums::timing;
+ }
+
+ /**
+ * Should caches be bypassed?
+ *
+ * Some CPUs need to bypass caches to allow direct memory
+ * accesses, which is required for hardware virtualization.
+ */
+ bool bypassCaches() const {
+ return memoryMode == Enums::atomic_noncaching;
}
+ /** @} */
+
+ /** @{ */
+ /**
+ * Get the memory mode of the system.
+ *
+ * \warn This should only be used by the Python world. The C++
+ * world should use one of the query functions above
+ * (isAtomicMode(), isTimingMode(), bypassCaches()).
+ */
+ Enums::MemoryMode getMemoryMode() const { return memoryMode; }
- /** Change the memory mode of the system. This should only be called by the
- * python!!
- * @param mode Mode to change to (atomic/timing)
+ /**
+ * Change the memory mode of the system.
+ *
+ * \warn This should only be called by the Python!
+ *
+ * @param mode Mode to change to (atomic/timing/...)
*/
void setMemoryMode(Enums::MemoryMode mode);
+ /** @} */
- PhysicalMemory *physmem;
PCEventQueue pcEventQueue;
std::vector<ThreadContext *> threadContexts;
* system. These threads could be Active or Suspended. */
int numRunningContexts();
- /** List to store ranges of memories in this system */
- AddrRangeList memRanges;
-
- /** check if an address points to valid system memory
- * and thus we can fetch instructions out of it
- */
- bool isMemory(const Addr addr) const;
-
Addr pagePtr;
uint64_t init_param;
/** Port to physical memory used for writing object files into ram at
* boot.*/
- FunctionalPort *functionalPort;
- VirtualPort *virtPort;
+ PortProxy physProxy;
+ FSTranslatingPortProxy virtProxy;
/** kernel symbol table */
SymbolTable *kernelSymtab;
return nextPID++;
}
+ /** Get a pointer to access the physical memory of the system */
+ PhysicalMemory& getPhysMem() { return physmem; }
+
/** Amount of physical memory that is still free */
- Addr freeMemSize();
+ Addr freeMemSize() const;
/** Amount of physical memory that exists */
- Addr memSize();
+ Addr memSize() const;
+
+ /**
+ * Check if a physical address is within a range of a memory that
+ * is part of the global address map.
+ *
+ * @param addr A physical address
+ * @return Whether the address corresponds to a memory
+ */
+ bool isMemAddr(Addr addr) const;
protected:
+
+ PhysicalMemory physmem;
+
Enums::MemoryMode memoryMode;
uint64_t workItemsBegin;
uint64_t workItemsEnd;
+ uint32_t numWorkIds;
std::vector<bool> activeCpus;
+ /** This array is a per-sytem list of all devices capable of issuing a
+ * memory system request and an associated string for each master id.
+ * It's used to uniquely id any master in the system by name for things
+ * like cache statistics.
+ */
+ std::vector<std::string> masterIds;
+
public:
+
+ /** Request an id used to create a request object in the system. All objects
+ * that intend to issues requests into the memory system must request an id
+ * in the init() phase of startup. All master ids must be fixed by the
+ * regStats() phase that immediately preceeds it. This allows objects in the
+ * memory system to understand how many masters may exist and
+ * appropriately name the bins of their per-master stats before the stats
+ * are finalized
+ */
+ MasterID getMasterId(std::string req_name);
+
+ /** Get the name of an object for a given request id.
+ */
+ std::string getMasterName(MasterID master_id);
+
+ /** Get the number of masters registered in the system */
+ MasterID maxMasters()
+ {
+ return masterIds.size();
+ }
+
+ virtual void regStats();
/**
* Called by pseudo_inst to track the number of work items started by this
* system.
*/
- uint64_t
+ uint64_t
incWorkItemsBegin()
{
return ++workItemsBegin;
return count;
}
+ inline void workItemBegin(uint32_t tid, uint32_t workid)
+ {
+ std::pair<uint32_t,uint32_t> p(tid, workid);
+ lastWorkItemStarted[p] = curTick();
+ }
+
+ void workItemEnd(uint32_t tid, uint32_t workid);
+
/**
* Fix up an address used to match PCs for hooking simulator
* events on to target function executions. See comment in
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
- virtual void resume();
+
+ unsigned int drain(DrainManager *dm);
+ void drainResume();
public:
Counter totalNumInsts;
EventQueue instEventQueue;
+ std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
+ std::map<uint32_t, Stats::Histogram*> workItemStats;
////////////////////////////////////////////
//
static void printSystems();
+ // For futex system call
+ std::map<uint64_t, std::list<ThreadContext *> * > futexMap;
+
+ protected:
+
+ /**
+ * If needed, serialize additional symbol table entries for a
+ * specific subclass of this sytem. Currently this is used by
+ * Alpha and MIPS.
+ *
+ * @param os stream to serialize to
+ */
+ virtual void serializeSymtab(std::ostream &os) {}
+
+ /**
+ * If needed, unserialize additional symbol table entries for a
+ * specific subclass of this system.
+ *
+ * @param cp checkpoint to unserialize from
+ * @param section relevant section in the checkpoint
+ */
+ virtual void unserializeSymtab(Checkpoint *cp,
+ const std::string §ion) {}
};
+void printSystems();
+
#endif // __SYSTEM_HH__
projects / gem5.git / blobdiff