cpu: implements vector registers

[gem5.git] / src / sim / system.hh

diff --git a/src/sim/system.hh b/src/sim/system.hh
index 5b68373a6157353bca9596b15b1b86e0f903aaaa..97d271d3aa1aa1269317f96071c3c203f7ad4f47 100644 (file)
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2014 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -51,18 +51,26 @@
 #include <utility>
 #include <vector>
 
+#include "arch/isa_traits.hh"
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
 #include "base/statistics.hh"
-#include "cpu/pc_event.hh"
+#include "config/the_isa.hh"
 #include "enums/MemoryMode.hh"
-#include "kern/system_events.hh"
 #include "mem/mem_object.hh"
 #include "mem/port.hh"
 #include "mem/port_proxy.hh"
 #include "mem/physical.hh"
 #include "params/System.hh"
 
+/**
+ * To avoid linking errors with LTO, only include the header if we
+ * actually have the definition.
+ */
+#if THE_ISA != NULL_ISA
+#include "cpu/pc_event.hh"
+#endif
+
 class BaseCPU;
 class BaseRemoteGDB;
 class GDBListener;
@@ -91,7 +99,7 @@ class System : public MemObject
         { }
         bool recvTimingResp(PacketPtr pkt)
         { panic("SystemPort does not receive timing!\n"); return false; }
-        void recvRetry()
+        void recvReqRetry()
         { panic("SystemPort does not expect retry!\n"); }
     };
 
@@ -269,6 +277,21 @@ class System : public MemObject
      */
     bool isMemAddr(Addr addr) const;
 
+    /**
+     * Get the architecture.
+     */
+    Arch getArch() const { return Arch::TheISA; }
+
+     /**
+     * Get the page bytes for the ISA.
+     */
+    Addr getPageBytes() const { return TheISA::PageBytes; }
+
+    /**
+     * Get the number of bits worth of in-page adress for the ISA.
+     */
+    Addr getPageShift() const { return TheISA::PageShift; }
+
   protected:
 
     PhysicalMemory physmem;
@@ -494,11 +517,10 @@ class System : public MemObject
     int registerThreadContext(ThreadContext *tc, int assigned=-1);
     void replaceThreadContext(ThreadContext *tc, int context_id);
 
-    void serialize(std::ostream &os);
-    void unserialize(Checkpoint *cp, const std::string &section);
+    void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+    void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
 
-    unsigned int drain(DrainManager *dm);
-    void drainResume();
+    void drainResume() M5_ATTR_OVERRIDE;
 
   public:
     Counter totalNumInsts;
@@ -529,7 +551,7 @@ class System : public MemObject
      *
      * @param os stream to serialize to
      */
-    virtual void serializeSymtab(std::ostream &os) {}
+    virtual void serializeSymtab(CheckpointOut &os) const {}
 
     /**
      * If needed, unserialize additional symbol table entries for a
@@ -538,8 +560,7 @@ class System : public MemObject
      * @param cp checkpoint to unserialize from
      * @param section relevant section in the checkpoint
      */
-    virtual void unserializeSymtab(Checkpoint *cp,
-                                   const std::string &section) {}
+    virtual void unserializeSymtab(CheckpointIn &cp) {}
 
 };