#include "base/misc.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
-#include "kern/system_events.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/port_proxy.hh"
#include "mem/physical.hh"
#include "params/System.hh"
+/**
+ * To avoid linking errors with LTO, only include the header if we
+ * actually have the definition.
+ */
+#if THE_ISA != NULL_ISA
+#include "cpu/pc_event.hh"
+#endif
+
class BaseCPU;
class BaseRemoteGDB;
class GDBListener;
SystemPort(const std::string &_name, MemObject *_owner)
: MasterPort(_name, _owner)
{ }
- bool recvTimingResp(PacketPtr pkt)
+ bool recvTimingResp(PacketPtr pkt) override
{ panic("SystemPort does not receive timing!\n"); return false; }
- void recvRetry()
+ void recvReqRetry() override
{ panic("SystemPort does not expect retry!\n"); }
};
* After all objects have been created and all ports are
* connected, check that the system port is connected.
*/
- virtual void init();
+ void init() override;
/**
* Get a reference to the system port that can be used by
* Additional function to return the Port of a memory object.
*/
BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
/** @{ */
/**
std::vector<ThreadContext *> threadContexts;
int _numContexts;
+ const bool multiThread;
- ThreadContext *getThreadContext(ThreadID tid)
+ ThreadContext *getThreadContext(ContextID tid)
{
return threadContexts[tid];
}
*/
bool isMemAddr(Addr addr) const;
+ /**
+ * Get the architecture.
+ */
+ Arch getArch() const { return Arch::TheISA; }
+
/**
* Get the page bytes for the ISA.
*/
return masterIds.size();
}
- virtual void regStats();
+ void regStats() override;
/**
* Called by pseudo_inst to track the number of work items started by this
* system.
System(Params *p);
~System();
- void initState();
+ void initState() override;
const Params *params() const { return (const Params *)_params; }
/// @return Starting address of first page
Addr allocPhysPages(int npages);
- int registerThreadContext(ThreadContext *tc, int assigned=-1);
- void replaceThreadContext(ThreadContext *tc, int context_id);
+ ContextID registerThreadContext(ThreadContext *tc,
+ ContextID assigned = InvalidContextID);
+ void replaceThreadContext(ThreadContext *tc, ContextID context_id);
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- unsigned int drain(DrainManager *dm);
- void drainResume();
+ void drainResume() override;
public:
Counter totalNumInsts;
*
* @param os stream to serialize to
*/
- virtual void serializeSymtab(std::ostream &os) {}
+ virtual void serializeSymtab(CheckpointOut &os) const {}
/**
* If needed, unserialize additional symbol table entries for a
* @param cp checkpoint to unserialize from
* @param section relevant section in the checkpoint
*/
- virtual void unserializeSymtab(Checkpoint *cp,
- const std::string §ion) {}
+ virtual void unserializeSymtab(CheckpointIn &cp) {}
};