/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
#include "base/misc.hh"
#include "mem/request.hh"
-#include "sim/faults.hh"
+#include "sim/fault_fwd.hh"
#include "sim/sim_object.hh"
class ThreadContext;
class Packet;
+class Port;
-class GenericTLB : public SimObject
+class BaseTLB : public SimObject
{
protected:
- GenericTLB(const std::string &name) : SimObject(name)
+ BaseTLB(const Params *p)
+ : SimObject(p)
{}
public:
- Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
+ enum Mode { Read, Write, Execute };
+
+ public:
+ virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
+
+ /** Get any port that the TLB or hardware table walker needs.
+ * This is used for migrating port connections during a takeOverFrom()
+ * call. */
+ virtual Port* getPort() { return NULL; }
+
+ class Translation
+ {
+ public:
+ virtual ~Translation()
+ {}
+
+ /**
+ * Signal that the translation has been delayed due to a hw page table
+ * walk.
+ */
+ virtual void markDelayed() = 0;
+
+ /*
+ * The memory for this object may be dynamically allocated, and it may
+ * be responsible for cleaning itself up which will happen in this
+ * function. Once it's called, the object is no longer valid.
+ */
+ virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ Mode mode) = 0;
+ };
+};
+
+class GenericTLB : public BaseTLB
+{
+ protected:
+ GenericTLB(const Params *p)
+ : BaseTLB(p)
+ {}
+
+ public:
+ void demapPage(Addr vaddr, uint64_t asn);
+
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode);
};
#endif // __ARCH_SPARC_TLB_HH__