merge alpha system files into tree

[gem5.git] / src / sim / tlb.hh

diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 8e291ecc996725c65b8f294e552d7f0d11fe0226..253f1207208f19c009f097b1190daca06591ef7a 100644 (file)
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -31,36 +43,68 @@
 #ifndef __SIM_TLB_HH__
 #define __SIM_TLB_HH__
 
+#include "base/misc.hh"
 #include "mem/request.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/sim_object.hh"
-#include "sim/faults.hh"
 
 class ThreadContext;
 class Packet;
+class Port;
 
-class GenericTLB : public SimObject
+class BaseTLB : public SimObject
 {
-  public:
-    GenericTLB(const std::string &name) : SimObject(name)
+  protected:
+    BaseTLB(const Params *p)
+        : SimObject(p)
     {}
-};
 
-class GenericITB : public GenericTLB
-{
   public:
-    GenericITB(const std::string &name) : GenericTLB(name)
-    {}
+    enum Mode { Read, Write, Execute };
 
-    Fault translate(RequestPtr &req, ThreadContext *tc);
+  public:
+    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
+
+    /** Get any port that the TLB or hardware table walker needs.
+     * This is used for migrating port connections during a takeOverFrom()
+     * call. */
+    virtual Port*  getPort() { return NULL; }
+
+    class Translation
+    {
+      public:
+        virtual ~Translation()
+        {}
+
+        /**
+         * Signal that the translation has been delayed due to a hw page table
+         * walk.
+         */
+        virtual void markDelayed() = 0;
+
+        /*
+         * The memory for this object may be dynamically allocated, and it may
+         * be responsible for cleaning itself up which will happen in this
+         * function. Once it's called, the object is no longer valid.
+         */
+        virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
+                            Mode mode) = 0;
+    };
 };
 
-class GenericDTB : public GenericTLB
+class GenericTLB : public BaseTLB
 {
-  public:
-    GenericDTB(const std::string &name) : GenericTLB(name)
+  protected:
+    GenericTLB(const Params *p)
+        : BaseTLB(p)
     {}
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+  public:
+    void demapPage(Addr vaddr, uint64_t asn);
+
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+                         Translation *translation, Mode mode);
 };
 
 #endif // __ARCH_SPARC_TLB_HH__