Merge remote-tracking branch 'origin/master'

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 92b7101ced8cd315ae98b6605e4d64dbf824ddaf..339b86f38a8e078c72981e875381aa96850b0860 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -4,6 +4,7 @@ import os
 from os.path import dirname, join
 from collections import namedtuple
 
+
 def find_wiki_file(name):
     filedir = os.path.dirname(os.path.abspath(__file__))
     basedir = dirname(dirname(dirname(filedir)))
@@ -47,16 +48,16 @@ def get_signal_name(name):
 @unique
 class Function(Enum):
     NONE = 0
-    ALU = 1<<1
-    LDST = 1<<2
-    SHIFT_ROT = 1<<3
-    LOGICAL = 1<<4
-    BRANCH = 1<<5
-    CR = 1<<6
-    TRAP = 1<<7
-    MUL = 1<<8
-    DIV = 1<<9
-    SPR = 1<<10
+    ALU = 1 << 1
+    LDST = 1 << 2
+    SHIFT_ROT = 1 << 3
+    LOGICAL = 1 << 4
+    BRANCH = 1 << 5
+    CR = 1 << 6
+    TRAP = 1 << 7
+    MUL = 1 << 8
+    DIV = 1 << 9
+    SPR = 1 << 10
 
 
 @unique
@@ -91,6 +92,7 @@ class Form(Enum):
     Z22 = 27
     Z23 = 28
 
+
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 _insns = [
@@ -132,7 +134,7 @@ for i, insn in enumerate(_insns):
 
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 @unique
-class InternalOp(Enum):
+class MicrOp(Enum):
     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
     OP_NOP = 1
     OP_ADD = 2
@@ -231,14 +233,14 @@ class In2Sel(Enum):
     CONST_SH = 10
     CONST_SH32 = 11
     SPR = 12
-    RS = 13 # for shiftrot (M-Form)
+    RS = 13  # for shiftrot (M-Form)
 
 
 @unique
 class In3Sel(Enum):
     NONE = 0
     RS = 1
-    RB = 2 # for shiftrot (M-Form)
+    RB = 2  # for shiftrot (M-Form)
 
 
 @unique
@@ -263,6 +265,7 @@ class LDSTMode(Enum):
     NONE = 0
     update = 1
     cix = 2
+    cx = 3
 
 
 @unique
@@ -278,6 +281,7 @@ class CryIn(Enum):
     ONE = 1
     CA = 2
 
+
 @unique
 class CRInSel(Enum):
     NONE = 0
@@ -288,6 +292,7 @@ class CRInSel(Enum):
     BC = 5
     WHOLE_REG = 6
 
+
 @unique
 class CROutSel(Enum):
     NONE = 0
@@ -321,13 +326,13 @@ XER_bits = {
     'CA': 34,
     'OV32': 44,
     'CA32': 45
-    }
+}
 
 if __name__ == '__main__':
     # find out what the heck is in SPR enum :)
-    print ("sprs", len(SPR))
-    print (dir(SPR))
-    print (dir(Enum))
-    print (SPR.__members__['TAR'])
+    print("sprs", len(SPR))
+    print(dir(SPR))
+    print(dir(Enum))
+    print(SPR.__members__['TAR'])
     for x in SPR:
-        print (x, x.value, str(x), x.name)
+        print(x, x.value, str(x), x.name)