add register specs to pipeline in/out so that they can be used to connect up

[soc.git] / src / soc / fu / cr / pipe_data.py

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 107a340e37211b73ac559bb1fb590058d08d302c..2b240263ab0cc9badbbeaa4e180cfba382c7bdb2 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -4,10 +4,12 @@ from soc.fu.alu.pipe_data import IntegerData
 
 
 class CRInputData(IntegerData):
+    regspec = [('INT', 'a', '0:63'),
+               ('CR', 'cr', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
-        self.cr = Signal(64, reset_less=True) # CR in
+        self.cr = Signal(32, reset_less=True) # CR in
 
     def __iter__(self):
         yield from super().__iter__()
@@ -20,10 +22,12 @@ class CRInputData(IntegerData):
                       self.cr.eq(i.cr)]
 
 class CROutputData(IntegerData):
+    regspec = [('INT', 'o', '0:63'),
+               ('CR', 'cr', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Signal(64, reset_less=True) # RA
-        self.cr = Signal(64, reset_less=True) # CR in
+        self.cr = Signal(32, reset_less=True) # CR in
 
     def __iter__(self):
         yield from super().__iter__()