from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
-from soc.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import IntegerData
class CRInputData(IntegerData):
+ regspec = [('INT', 'a', '0:63'),
+ ('CR', 'cr', '32')]
def __init__(self, pspec):
super().__init__(pspec)
self.a = Signal(64, reset_less=True) # RA
- self.cr = Signal(64, reset_less=True) # CR in
+ self.cr = Signal(32, reset_less=True) # CR in
def __iter__(self):
yield from super().__iter__()
self.cr.eq(i.cr)]
class CROutputData(IntegerData):
+ regspec = [('INT', 'o', '0:63'),
+ ('CR', 'cr', '32')]
def __init__(self, pspec):
super().__init__(pspec)
self.o = Signal(64, reset_less=True) # RA
- self.cr = Signal(64, reset_less=True) # CR in
+ self.cr = Signal(32, reset_less=True) # CR in
def __iter__(self):
yield from super().__iter__()