from soc.fu.mul.mul_input_record import CompMULOpSubset
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.pipe_data import ALUOutputData, ALUInputData
+from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
from nmigen import Signal
-class MulIntermediateData(ALUInputData):
+class MulIntermediateData(DivInputData):
def __init__(self, pspec):
super().__init__(pspec)
class MulOutputData(IntegerData):
regspec = [('INT', 'o', '0:128'),
- ('XER', 'xer_so', '32'), # XER bit 32: SO
- ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+ ('XER', 'xer_so', '32')] # XER bit 32: SO
def __init__(self, pspec):
super().__init__(pspec, False) # still input style
class MulPipeSpec(CommonPipeSpec):
- regspec = (ALUInputData.regspec, ALUOutputData.regspec)
+ regspec = (DivInputData.regspec, DivMulOutputData.regspec)
opsubsetkls = CompMULOpSubset