MultiCompUnit fixed to not need rdmask to be sustained indefinitely

[soc.git] / src / soc / simple / core.py

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index a37b9ba48dad5763fe3823f5129cde52c4239e85..1c67c87b3f5c783c72131918e4efff317babdb4c 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -70,6 +70,23 @@ def sort_fuspecs(fuspecs):
 
 
 class CoreInput:
+    """CoreInput: this is the input specification for Signals coming into core.
+
+    * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
+      (TODO: bigendian_i should really be read from the relevant MSR bit)
+
+    * the previously-decoded instruction goes into the Decode2Execute1Type
+      data structure. no need for Core to re-decode that.  however note
+      that *satellite* decoders *are* part of Core.
+
+    * the raw instruction. this is used by satellite decoders internal to
+      Core, to provide Function-Unit-specific information.  really, they
+      should be part of the actual ALU itself (in order to reduce wires),
+      but hey.
+
+    * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
+      Vector context, etc.
+    """
     def __init__(self, pspec, svp64_en, regreduce_en):
         self.pspec = pspec
         self.svp64_en = svp64_en
@@ -270,7 +287,11 @@ class NonProductionCore(ControlBase):
 
         # enable the required Function Unit based on the opcode decode
         # note: this *only* works correctly for simple core when one and
-        # *only* one FU is allocated per instruction
+        # *only* one FU is allocated per instruction.  what is actually
+        # required is one PriorityPicker per group of matching fnunits,
+        # and for only one actual FU to be "picked".  this basically means
+        # when ReservationStations are enabled it will be possible to
+        # monitor multiple outstanding processing properly.
         for funame, fu in fus.items():
             fnunit = fu.fnunit.value
             enable = Signal(name="en_%s" % funame, reset_less=True)
@@ -317,12 +338,12 @@ class NonProductionCore(ControlBase):
         for funame, fu in fus.items():
             with m.If(fu.busy_o):
                 comb += busy_o.eq(fu.busy_o)
-                # rdmask, which is for registers, needs to come
-                # from the *main* decoder
-                rdmask = get_rdflags(self.i.e, fu)
-                comb += fu.rdmaskn.eq(~rdmask)
 
         # set ready/valid signalling.  if busy, means refuse incoming issue
+        # XXX note: for an in-order core this is far too simple.  busy must
+        # be gated with the *availability* of the incoming (requested)
+        # instruction, where Core must be prepared to store-and-hold
+        # an instruction if no FU is available.
         comb += self.p.o_ready.eq(~busy_o)
 
         return fu_bitdict