fix(iomux): Fix port signal length (given mux size non-power of 2)

[pinmux.git] / src / spec / i_class.py

diff --git a/src/spec/i_class.py b/src/spec/i_class.py
index daf064a6b76b321ee189bbdb7abcde36aa3a2176..8a0196db484c14660c07a6a23772c6ec4a5b7d74 100644 (file)
--- a/src/spec/i_class.py
+++ b/src/spec/i_class.py
@@ -8,7 +8,10 @@ from spec.ifaceprint import display_fixed
 
 def pinspec():
     pinbanks = {
-        'A': 28,
+        'A': (28, 4),
+        'B': (18, 4),
+        'C': (24, 1),
+        'D': (93, 1),
     }
     fixedpins = {
         'CTRL_SYS': [
@@ -36,11 +39,11 @@ def pinspec():
                       'JTAG': 'JTAG (JTAG_SEL=HI/LO)',
                       'LCD': '24-pin RGB/TTL LCD',
                       'RG': 'RGMII Ethernet',
-                      'MMC': 'eMMC 1/2/4/8 pin',
+                      'EMMC': 'eMMC 1/2/4/8 pin',
                       'PWM': 'PWM (pulse-width modulation)',
-                      'SD0': 'SD/MMC 0',
-                      'SD1': 'SD/MMC 1',
-                      'SD2': 'SD/MMC 2',
+                      'MMC0': 'SD/MMC 0',
+                      'MMC1': 'SD/MMC 1',
+                      'MMC2': 'SD/MMC 2',
                       'MSPI0': 'SPI (Serial Peripheral Interface) Master 0',
                       'MSPI1': 'SPI (Serial Peripheral Interface) Master 1',
                       'MQSPI': 'Quad SPI Master 0',
@@ -58,7 +61,16 @@ def pinspec():
                       }
 
     ps = PinSpec(pinbanks, fixedpins, function_names,
-                 ['lcd0', 'jtag0'])
+                 {'lcd': {'bus': 'fastbus',
+                          'mmap': [['Cfg', 0x20000, 10]
+                                   ]},
+                  'jtag': {'bus': 'fastbus'},
+                  'fb': {'bus': 'fastbus'},
+                  'sdr': {'bus': 'fastbus',
+                          'mmap': [['Mem', 0x70000000, 0x400000],
+                                   ['Cfg', 0x17000, 12]
+                                   ]},
+                  })
 
     # Bank A, 0-27
     ps.gpio("", ('A', 0), 0, 0, 28)
@@ -82,6 +94,26 @@ def pinspec():
     ps.uart("1", ('A', 2), 2)
     ps.uart("2", ('A', 14), 2)
 
+    # see comment in spec.interfaces.PinGen, this is complicated.
+    flexspec = {
+        #'FB_TS': ('FB_ALE', 2), # commented out for now
+        'FB_CS2': ('FB_BWE2', 2),
+        'FB_AD0': ('FB_BWE2', 3),
+        'FB_CS3': ('FB_BWE3', 2),
+        'FB_AD1': ('FB_BWE3', 3),
+        'FB_TBST': ('FB_OE', 2),
+        'FB_TSIZ0': ('FB_BWE0', 2),
+        'FB_TSIZ1': ('FB_BWE1', 2),
+    }
+    ps.gpio("", ('B', 0), 0, 0, 18)
+    ps.flexbus1("", ('B', 0), 1, spec=flexspec)
+    ps.emmc("", ('B', 0), 3)
+
+    ps.flexbus2("", ('C', 0), 0)
+
+    ps.sdram1("", ('D', 0), 0)
+    ps.sdram3("", ('D', 36), 0)
+
     # Scenarios below can be spec'd out as either "find first interface"
     # by name/number e.g. SPI1, or as "find in bank/mux" which must be
     # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
@@ -89,16 +121,16 @@ def pinspec():
     # using "BM:Name".  Pins are removed in-order as listed from
     # lists (interfaces, EINTs, PWMs) from available pins.
 
-    i_class = ['ULPI0/8', 'ULPI1', 'MMC', 'SD0', 'UART0',
-                'TWI0', 'MSPI0', 'B3:SD1', ]
+    i_class = ['ULPI0/8', 'ULPI1', 'EMMC', 'MMC0', 'UART0',
+               'TWI0', 'MSPI0', 'B3:MMC1', ]
     i_class_eint = ['EINT_0', 'EINT_1', 'EINT_2', 'EINT_3', 'EINT_4']
     i_class_pwm = ['B2:PWM_0']
     descriptions = {
-        'MMC': 'internal (on Card)',
+        'EMMC': 'internal (on Card)',
         'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
         'and UART2, for debug purposes',
         'TWI2': 'I2C.\n',
-        'E2:SD1': '',
+        'E2:MMC1': '',
         'MSPI1': '',
         'UART0': '',
         'B1:LCD/22': '18-bit RGB/TTL LCD',