move GPIO and JTAG a little bit on E side (for RGMII interface 1)

[pinmux.git] / src / spec / ls2.py

diff --git a/src/spec/ls2.py b/src/spec/ls2.py
index caec431edcc5b74742d795f8af97f4646cf7bb4b..54916818b22f536d53d2e7f03814e32e2b7769b2 100644 (file)
--- a/src/spec/ls2.py
+++ b/src/spec/ls2.py
@@ -38,6 +38,7 @@ def pinspec():
         ]}
     fixedpins = {}
     function_names = {
+                      'RG0': 'Gigabit Ethernet 0',
                       'PWM': 'PWM (pulse-width modulation)',
                       'MSPI0': 'SPI Master 1 (general)',
                       'MSPI1': 'SPI Master 2 (SDCard)',
@@ -84,14 +85,13 @@ def pinspec():
     ps.uart("0", ('S', 26), 0)
     ps.mspi("0", ('S', 28), 0)
 
-    ps.gpio("", ('E', 0), 0, 0, 6) # GPIO 0-5
-    ps.vss("E", ('E', 6), 0, 4, 1)
-    ps.vdd("E", ('E', 7), 0, 4, 1)
-    ps.vdd("I", ('E', 8), 0, 4, 1)
-    ps.vss("I", ('E', 9), 0, 4, 1)
-    ps.gpio("", ('E', 10), 0, 6, 3) # GPIO 6-8
-    ps.jtag("", ('E', 13), 0, 0, 4)
-    ps.gpio("", ('E', 17), 0, 9, 5) # GPIO 9-13
+    ps.gpio("", ('E', 0), 0, 0, 4) # GPIO 0-3
+    ps.vss("E", ('E', 4), 0, 4, 1)
+    ps.vdd("E", ('E', 5), 0, 4, 1)
+    ps.vdd("I", ('E', 6), 0, 4, 1)
+    ps.vss("I", ('E', 7), 0, 4, 1)
+    ps.gpio("", ('E', 8), 0, 6, 10) # GPIO 4-13
+    ps.jtag("", ('E', 18), 0, 0, 4)
     ps.vss("I", ('E', 22), 0, 5, 1)
     ps.vdd("I", ('E', 23), 0, 5, 1)
     ps.vss("E", ('E', 24), 0, 5, 1)
@@ -99,19 +99,21 @@ def pinspec():
     ps.gpio("", ('E', 26), 0, 14, 2) # GPIO 14-15
     ps.eint("", ('E', 28), 0, 0, 3)
     ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
+    #ps.rgmii("1", ('E', 0), 0, 0, 4)
 
-    ps.vss("E", ('N', 6), 0, 6, 1)
-    ps.vdd("E", ('N', 7), 0, 6, 1)
-    ps.vdd("I", ('N', 8), 0, 6, 1)
-    ps.vss("I", ('N', 9), 0, 6, 1)
+    ps.vss("E", ('N', 1), 0, 6, 1)
+    ps.vdd("E", ('N', 2), 0, 6, 1)
+    ps.vdd("I", ('N', 3), 0, 6, 1)
+    ps.vss("I", ('N', 4), 0, 6, 1)
+    ps.rgmii("0", ('N', 5), 0, 0, 18)
     #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
     #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
     #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
     ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
-    ps.vss("I", ('N', 22), 0, 7, 1)
-    ps.vdd("I", ('N', 23), 0, 7, 1)
-    ps.vss("E", ('N', 24), 0, 7, 1)
-    ps.vdd("E", ('N', 25), 0, 7, 1)
+    ps.vss("I", ('N', 23), 0, 7, 1)
+    ps.vdd("I", ('N', 24), 0, 7, 1)
+    ps.vss("E", ('N', 25), 0, 7, 1)
+    ps.vdd("E", ('N', 26), 0, 7, 1)
 
     #ps.mquadspi("1", ('S', 0), 0)