ir3: Set up full/half register conflicts correctly

[mesa.git] / src / util / register_allocate.c

diff --git a/src/util/register_allocate.c b/src/util/register_allocate.c
index b23bb3772923db439f83513fb111595570aac9ef..352736304599100178c71a84dae40f7dbe289e66 100644 (file)
--- a/src/util/register_allocate.c
+++ b/src/util/register_allocate.c
@@ -304,6 +304,31 @@ ra_add_transitive_reg_conflict(struct ra_regs *regs,
    }
 }
 
+/**
+ * Set up conflicts between base_reg and it's two half registers reg0 and
+ * reg1, but take care to not add conflicts between reg0 and reg1.
+ *
+ * This is useful for architectures where full size registers are aliased by
+ * two half size registers (eg 32 bit float and 16 bit float registers).
+ */
+void
+ra_add_transitive_reg_pair_conflict(struct ra_regs *regs,
+                                    unsigned int base_reg, unsigned int reg0, unsigned int reg1)
+{
+   unsigned int i;
+
+   ra_add_reg_conflict(regs, reg0, base_reg);
+   ra_add_reg_conflict(regs, reg1, base_reg);
+
+   for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
+      unsigned int conflict = regs->regs[base_reg].conflict_list[i];
+      if (conflict != reg1)
+         ra_add_reg_conflict(regs, reg0, regs->regs[base_reg].conflict_list[i]);
+      if (conflict != reg0)
+         ra_add_reg_conflict(regs, reg1, regs->regs[base_reg].conflict_list[i]);
+   }
+}
+
 /**
  * Makes every conflict on the given register transitive.  In other words,
  * every register that conflicts with r will now conflict with every other