#include <stdbool.h>
#include <pthread.h>
#include <assert.h>
+#include <stdint.h>
#include <i915_drm.h>
#ifdef HAVE_VALGRIND
#include "util/macros.h"
#include "util/list.h"
+/* Pre-declarations needed for WSI entrypoints */
+struct wl_surface;
+struct wl_display;
+typedef struct xcb_connection_t xcb_connection_t;
+typedef uint32_t xcb_visualid_t;
+typedef uint32_t xcb_window_t;
+
+#define VK_USE_PLATFORM_XCB_KHR
+#define VK_USE_PLATFORM_WAYLAND_KHR
+
#define VK_PROTOTYPES
#include <vulkan/vulkan.h>
#include <vulkan/vulkan_intel.h>
-#include <vulkan/vk_ext_khr_swapchain.h>
-#include <vulkan/vk_ext_khr_device_swapchain.h>
#include "anv_entrypoints.h"
#include "anv_gen_macros.h"
__anv_vector_offset += (queue)->element_size)
struct anv_bo {
- int gem_handle;
+ uint32_t gem_handle;
/* Index into the current validation list. This is used by the
* validation list building alrogithm to track which buffers are already
uint32_t end;
};
+#define CACHELINE_SIZE 64
+#define CACHELINE_MASK 63
+
+static void inline
+anv_state_clflush(struct anv_state state)
+{
+ /* state.map may not be cacheline aligned, so round down the start pointer
+ * to a cacheline boundary so we flush all pages that contain the state.
+ */
+ void *end = state.map + state.alloc_size;
+ void *p = (void *) (((uintptr_t) state.map) & ~CACHELINE_MASK);
+
+ __builtin_ia32_sfence();
+ while (p < end) {
+ __builtin_ia32_clflush(p);
+ p += CACHELINE_SIZE;
+ }
+}
+
void anv_block_pool_init(struct anv_block_pool *pool,
struct anv_device *device, uint32_t block_size);
void anv_block_pool_finish(struct anv_block_pool *pool);
struct isl_device isl_dev;
};
-bool anv_is_scalar_shader_stage(const struct brw_compiler *compiler,
- VkShaderStage stage);
-
struct anv_instance {
VK_LOADER_DATA _loader_data;
int physicalDeviceCount;
struct anv_physical_device physicalDevice;
- struct anv_wsi_implementation * wsi_impl[VK_PLATFORM_NUM_KHR];
+ void * wayland_wsi;
};
VkResult anv_init_wsi(struct anv_instance *instance);
};
void* anv_gem_mmap(struct anv_device *device,
- uint32_t gem_handle, uint64_t offset, uint64_t size);
+ uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
void anv_gem_munmap(void *p, uint64_t size);
uint32_t anv_gem_create(struct anv_device *device, size_t size);
-void anv_gem_close(struct anv_device *device, int gem_handle);
-int anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
-int anv_gem_wait(struct anv_device *device, int gem_handle, int64_t *timeout_ns);
+void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
+uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
+int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
int anv_gem_execbuffer(struct anv_device *device,
struct drm_i915_gem_execbuffer2 *execbuf);
-int anv_gem_set_tiling(struct anv_device *device, int gem_handle,
+int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
uint32_t stride, uint32_t tiling);
int anv_gem_create_context(struct anv_device *device);
int anv_gem_destroy_context(struct anv_device *device, int context);
int anv_gem_get_param(int fd, uint32_t param);
int anv_gem_get_aperture(int fd, uint64_t *size);
-int anv_gem_handle_to_fd(struct anv_device *device, int gem_handle);
-int anv_gem_fd_to_handle(struct anv_device *device, int fd);
-int anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
+int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
+uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
+int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
+int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
+ uint32_t read_domains, uint32_t write_domain);
VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
} while (0)
+#define anv_state_pool_emit(pool, cmd, align, ...) ({ \
+ const uint32_t __size = __anv_cmd_length(cmd) * 4; \
+ struct anv_state __state = \
+ anv_state_pool_alloc((pool), __size, align); \
+ struct cmd __template = { \
+ __VA_ARGS__ \
+ }; \
+ __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
+ VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
+ if (!(pool)->block_pool->device->info.has_llc) \
+ anv_state_clflush(__state); \
+ __state; \
+ })
+
#define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
.GraphicsDataTypeGFDT = 0, \
.LLCCacheabilityControlLLCCC = 0, \
struct anv_device_memory {
struct anv_bo bo;
+ uint32_t type_index;
VkDeviceSize map_size;
void * map;
};
/* Index into the sampler table for the associated sampler */
int16_t sampler_index;
- } stage[VK_SHADER_STAGE_NUM];
+
+ /* Index into the image table for the associated image */
+ int16_t image_index;
+ } stage[MESA_SHADER_STAGES];
/* Immutable samplers (or NULL if no immutable samplers) */
struct anv_sampler **immutable_samplers;
struct anv_sampler *sampler;
};
+ struct anv_buffer_view *buffer_view;
+
struct {
struct anv_buffer *buffer;
uint64_t offset;
struct {
uint32_t surface_start;
uint32_t sampler_start;
- } stage[VK_SHADER_STAGE_NUM];
+ uint32_t image_start;
+ } stage[MESA_SHADER_STAGES];
} set[MAX_SETS];
uint32_t num_sets;
struct anv_pipeline_binding *surface_to_descriptor;
uint32_t sampler_count;
struct anv_pipeline_binding *sampler_to_descriptor;
- } stage[VK_SHADER_STAGE_NUM];
+ uint32_t image_count;
+ } stage[MESA_SHADER_STAGES];
struct anv_pipeline_binding entries[0];
};
uint32_t restart_index;
struct anv_vertex_binding vertex_bindings[MAX_VBS];
struct anv_descriptor_set * descriptors[MAX_SETS];
- struct anv_push_constants * push_constants[VK_SHADER_STAGE_NUM];
+ struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
struct anv_dynamic_state dynamic;
struct {
void gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
- uint32_t *a, uint32_t dwords,
- uint32_t alignment);
+ const void *data, uint32_t size, uint32_t alignment);
struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
uint32_t *a, uint32_t *b,
uint32_t dwords, uint32_t alignment);
struct anv_state
anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
- VkShaderStage stage);
+ gl_shader_stage stage);
+struct anv_state
+anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
void anv_cmd_buffer_clear_attachments(struct anv_cmd_buffer *cmd_buffer,
struct anv_render_pass *pass,
char data[0];
};
-struct anv_shader {
- struct anv_shader_module * module;
- char entrypoint[0];
-};
+static inline gl_shader_stage
+vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
+{
+ assert(__builtin_popcount(vk_stage) == 1);
+ return ffs(vk_stage) - 1;
+}
+
+static inline VkShaderStageFlagBits
+mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
+{
+ return (1 << mesa_stage);
+}
+
+#define anv_foreach_stage(stage, stage_bits) \
+ for (gl_shader_stage stage, __tmp = (gl_shader_stage)(stage_bits);\
+ stage = __builtin_ffs(__tmp) - 1, __tmp; \
+ __tmp &= ~(1 << (stage)))
struct anv_pipeline {
struct anv_device * device;
struct brw_gs_prog_data gs_prog_data;
struct brw_cs_prog_data cs_prog_data;
bool writes_point_size;
- struct brw_stage_prog_data * prog_data[VK_SHADER_STAGE_NUM];
- uint32_t scratch_start[VK_SHADER_STAGE_NUM];
+ struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
+ uint32_t scratch_start[MESA_SHADER_STAGES];
uint32_t total_scratch;
struct {
uint32_t vs_start;
VkResult
anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
const VkComputePipelineCreateInfo *info,
- struct anv_shader *shader);
+ struct anv_shader_module *module,
+ const char *entrypoint_name);
VkResult
anv_graphics_pipeline_create(VkDevice device,
bool has_stencil;
};
-/**
- * Stencil formats are often a special case. To reduce the number of lookups
- * into the VkFormat-to-anv_format translation table when working with
- * stencil, here is the handle to the table's entry for VK_FORMAT_S8_UINT.
- */
-extern const struct anv_format *const anv_format_s8_uint;
-
const struct anv_format *
anv_format_for_vk_format(VkFormat format);
+enum isl_format
+anv_get_isl_format(VkFormat format, VkImageAspectFlags aspect);
+
static inline bool
anv_format_is_color(const struct anv_format *format)
{
return format->depth_format || format->has_stencil;
}
-struct anv_image_view_info {
- uint8_t surface_type; /**< RENDER_SURFACE_STATE.SurfaceType */
- bool is_array:1; /**< RENDER_SURFACE_STATE.SurfaceArray */
- bool is_cube:1; /**< RENDER_SURFACE_STATE.CubeFaceEnable* */
-};
-
-struct anv_image_view_info
-anv_image_view_info_for_vk_image_view_type(VkImageViewType type);
-
/**
- * A proxy for the color surfaces, depth surfaces, and stencil surfaces.
+ * Subsurface of an anv_image.
*/
struct anv_surface {
+ struct isl_surf isl;
+
/**
* Offset from VkImage's base address, as bound by vkBindImageMemory().
*/
uint32_t offset;
-
- uint32_t stride; /**< RENDER_SURFACE_STATE.SurfacePitch */
- uint16_t qpitch; /**< RENDER_SURFACE_STATE.QPitch */
-
- /**
- * \name Alignment of miptree images, in units of pixels.
- *
- * These fields contain the real alignment values, not the values to be
- * given to the GPU. For example, if h_align is 4, then program the GPU
- * with HALIGN_4.
- * \{
- */
- uint8_t h_align; /**< RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
- uint8_t v_align; /**< RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
- /** \} */
-
- enum isl_tiling tiling;
};
struct anv_image {
struct anv_bo *bo;
VkDeviceSize offset;
- uint8_t surface_type; /**< RENDER_SURFACE_STATE.SurfaceType */
-
bool needs_nonrt_surface_state:1;
bool needs_color_rt_surface_state:1;
+ bool needs_storage_surface_state:1;
/**
* Image subsurfaces
/** RENDER_SURFACE_STATE when using image as a non render target. */
struct anv_state nonrt_surface_state;
+
+ /** RENDER_SURFACE_STATE when using image as a storage image. */
+ struct anv_state storage_surface_state;
};
struct anv_image_create_info {
const VkImageCreateInfo *vk_info;
- bool force_tiling;
- enum isl_tiling tiling;
+ isl_tiling_flags_t isl_tiling_flags;
uint32_t stride;
};
const VkImageViewCreateInfo* pCreateInfo,
struct anv_cmd_buffer *cmd_buffer);
+struct anv_buffer_view {
+ struct anv_bo *bo;
+ uint32_t offset; /**< Offset into bo. */
+
+ struct anv_state surface_state;
+};
+
void anv_fill_buffer_surface_state(struct anv_device *device, void *state,
const struct anv_format *format,
uint32_t offset, uint32_t range,
uint32_t offset, uint32_t range,
uint32_t stride);
+void anv_image_view_fill_image_param(struct anv_device *device,
+ struct anv_image_view *view,
+ struct brw_image_param *param);
+
struct anv_sampler {
uint32_t state[4];
};
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
+ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
-ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader, VkShader)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
#define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
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