{
const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
pipeline->vs_prog_data.uses_instanceid;
- const uint32_t element_count = info->attributeCount + (sgvs ? 1 : 0);
+ const uint32_t element_count =
+ info->vertexAttributeDescriptionCount + (sgvs ? 1 : 0);
const uint32_t num_dwords = 1 + element_count * 2;
uint32_t *p;
- if (info->attributeCount == 0 && !sgvs)
+ if (info->vertexAttributeDescriptionCount == 0 && !sgvs)
return;
p = anv_batch_emitn(&pipeline->batch, num_dwords,
GEN7_3DSTATE_VERTEX_ELEMENTS);
- for (uint32_t i = 0; i < info->attributeCount; i++) {
+ for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
const VkVertexInputAttributeDescription *desc =
&info->pVertexAttributeDescriptions[i];
const struct anv_format *format = anv_format_for_vk_format(desc->format);
.Valid = true,
.SourceElementFormat = format->surface_format,
.EdgeFlagEnable = false,
- .SourceElementOffset = desc->offsetInBytes,
+ .SourceElementOffset = desc->offset,
.Component0Control = VFCOMP_STORE_SRC,
.Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
.Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
.Component2Control = VFCOMP_STORE_VID,
.Component3Control = VFCOMP_STORE_IID
};
- GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->attributeCount * 2], &element);
+ GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->vertexAttributeDescriptionCount * 2], &element);
}
}
static void
gen7_emit_rs_state(struct anv_pipeline *pipeline,
- const VkPipelineRasterStateCreateInfo *info,
+ const VkPipelineRasterizationStateCreateInfo *info,
const struct anv_graphics_pipeline_create_info *extra)
{
struct GEN7_3DSTATE_SF sf = {
[VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
[VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
[VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
- [VK_COMPARE_OP_LESS_EQUAL] = PREFILTEROPLEQUAL,
+ [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
[VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
[VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
- [VK_COMPARE_OP_GREATER_EQUAL] = PREFILTEROPGEQUAL,
+ [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
[VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
};
[VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
[VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
[VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
- [VK_STENCIL_OP_INC_CLAMP] = STENCILOP_INCRSAT,
- [VK_STENCIL_OP_DEC_CLAMP] = STENCILOP_DECRSAT,
+ [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
+ [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
[VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
- [VK_STENCIL_OP_INC_WRAP] = STENCILOP_INCR,
- [VK_STENCIL_OP_DEC_WRAP] = STENCILOP_DECR,
+ [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
+ [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
};
static const uint32_t vk_to_gen_blend_op[] = {
[VK_LOGIC_OP_AND] = LOGICOP_AND,
[VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
[VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
- [VK_LOGIC_OP_NOOP] = LOGICOP_NOOP,
+ [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
[VK_LOGIC_OP_XOR] = LOGICOP_XOR,
[VK_LOGIC_OP_OR] = LOGICOP_OR,
[VK_LOGIC_OP_NOR] = LOGICOP_NOR,
- [VK_LOGIC_OP_EQUIV] = LOGICOP_EQUIV,
+ [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
[VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
[VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
[VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
};
static const uint32_t vk_to_gen_blend[] = {
- [VK_BLEND_ZERO] = BLENDFACTOR_ZERO,
- [VK_BLEND_ONE] = BLENDFACTOR_ONE,
- [VK_BLEND_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
- [VK_BLEND_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
- [VK_BLEND_DEST_COLOR] = BLENDFACTOR_DST_COLOR,
- [VK_BLEND_ONE_MINUS_DEST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
- [VK_BLEND_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
- [VK_BLEND_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
- [VK_BLEND_DEST_ALPHA] = BLENDFACTOR_DST_ALPHA,
- [VK_BLEND_ONE_MINUS_DEST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
- [VK_BLEND_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
- [VK_BLEND_ONE_MINUS_CONSTANT_COLOR] = BLENDFACTOR_INV_CONST_COLOR,
- [VK_BLEND_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
- [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA] = BLENDFACTOR_INV_CONST_ALPHA,
- [VK_BLEND_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
- [VK_BLEND_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
- [VK_BLEND_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
- [VK_BLEND_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
- [VK_BLEND_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
+ [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
+ [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
+ [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
+ [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
+ [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
+ [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
+ [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
+ [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
+ [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
+ [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
+ [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
+ [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR] = BLENDFACTOR_INV_CONST_COLOR,
+ [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
+ [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA] = BLENDFACTOR_INV_CONST_ALPHA,
+ [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
+ [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
+ [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
+ [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
+ [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
};
static void
.DoubleSidedStencilEnable = true,
.StencilTestEnable = info->stencilTestEnable,
- .StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
- .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
- .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
- .StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
-
- .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
- .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
- .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
- .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
+ .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
+ .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
+ .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
+ .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
+
+ .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
+ .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
+ .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
+ .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
};
GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
static void
gen7_emit_cb_state(struct anv_pipeline *pipeline,
- const VkPipelineColorBlendStateCreateInfo *info)
+ const VkPipelineColorBlendStateCreateInfo *info,
+ const VkPipelineMultisampleStateCreateInfo *ms_info)
{
struct anv_device *device = pipeline->device;
struct GEN7_BLEND_STATE blend_state = {
.ColorBufferBlendEnable = a->blendEnable,
.IndependentAlphaBlendEnable = true, /* FIXME: yes? */
- .AlphaBlendFunction = vk_to_gen_blend_op[a->blendOpAlpha],
+ .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
- .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcBlendAlpha],
- .DestinationAlphaBlendFactor = vk_to_gen_blend[a->destBlendAlpha],
+ .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
+ .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
- .ColorBlendFunction = vk_to_gen_blend_op[a->blendOpColor],
- .SourceBlendFactor = vk_to_gen_blend[a->srcBlendColor],
- .DestinationBlendFactor = vk_to_gen_blend[a->destBlendColor],
- .AlphaToCoverageEnable = info->alphaToCoverageEnable,
+ .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
+ .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
+ .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
+ .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
# if 0
bool AlphaToOneEnable;
bool AlphaToCoverageDitherEnable;
# endif
- .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
- .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
- .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
- .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
+ .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
+ .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
+ .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
+ .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
.LogicOpEnable = info->logicOpEnable,
.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
assert(pCreateInfo->pVertexInputState);
gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
- assert(pCreateInfo->pRasterState);
- gen7_emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
+ assert(pCreateInfo->pRasterizationState);
+ gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
- gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
+ gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
+ pCreateInfo->pMultisampleState);
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
.StatisticsEnable = true);
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
- const VkPipelineRasterStateCreateInfo *rs_info = pCreateInfo->pRasterState;
+ const VkPipelineRasterizationStateCreateInfo *rs_info =
+ pCreateInfo->pRasterizationState;
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
.FrontWinding = vk_to_gen_front_face[rs_info->frontFace],
projects / mesa.git / blobdiff