#include "gen7_pack.h"
#include "gen75_pack.h"
+#include "genX_pipeline_util.h"
+
static void
-gen7_emit_vertex_input(struct anv_pipeline *pipeline,
- const VkPipelineVertexInputStateCreateInfo *info)
+emit_vertex_input(struct anv_pipeline *pipeline,
+ const VkPipelineVertexInputStateCreateInfo *info,
+ const struct anv_graphics_pipeline_create_info *extra)
{
- const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
- pipeline->vs_prog_data.uses_instanceid;
- const uint32_t element_count =
- info->vertexAttributeDescriptionCount + (sgvs ? 1 : 0);
- const uint32_t num_dwords = 1 + element_count * 2;
- uint32_t *p;
-
- if (info->vertexAttributeDescriptionCount == 0 && !sgvs)
+ uint32_t elements;
+ if (extra && extra->disable_vs) {
+ /* If the VS is disabled, just assume the user knows what they're
+ * doing and apply the layout blindly. This can only come from
+ * meta, so this *should* be safe.
+ */
+ elements = 0;
+ for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
+ elements |= (1 << info->pVertexAttributeDescriptions[i].location);
+ } else {
+ /* Pull inputs_read out of the VS prog data */
+ uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
+ assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
+ elements = inputs_read >> VERT_ATTRIB_GENERIC0;
+ }
+
+ uint32_t vb_count = __builtin_popcount(elements);
+
+ if (pipeline->vs_prog_data.uses_vertexid ||
+ pipeline->vs_prog_data.uses_instanceid)
+ vb_count++;
+
+ if (vb_count == 0)
return;
- p = anv_batch_emitn(&pipeline->batch, num_dwords,
- GEN7_3DSTATE_VERTEX_ELEMENTS);
+ const uint32_t num_dwords = 1 + vb_count * 2;
+
+ uint32_t *p = anv_batch_emitn(&pipeline->batch, num_dwords,
+ GEN7_3DSTATE_VERTEX_ELEMENTS);
+ memset(p + 1, 0, (num_dwords - 1) * 4);
for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
const VkVertexInputAttributeDescription *desc =
&info->pVertexAttributeDescriptions[i];
- const struct anv_format *format = anv_format_for_vk_format(desc->format);
+ enum isl_format format = anv_get_isl_format(desc->format,
+ VK_IMAGE_ASPECT_COLOR_BIT,
+ VK_IMAGE_TILING_LINEAR);
+
+ assert(desc->binding < 32);
+
+ if ((elements & (1 << desc->location)) == 0)
+ continue; /* Binding unused */
+
+ uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
struct GEN7_VERTEX_ELEMENT_STATE element = {
.VertexBufferIndex = desc->binding,
.Valid = true,
- .SourceElementFormat = format->surface_format,
+ .SourceElementFormat = format,
.EdgeFlagEnable = false,
.SourceElementOffset = desc->offset,
- .Component0Control = VFCOMP_STORE_SRC,
- .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
+ .Component0Control = vertex_element_comp_control(format, 0),
+ .Component1Control = vertex_element_comp_control(format, 1),
+ .Component2Control = vertex_element_comp_control(format, 2),
+ .Component3Control = vertex_element_comp_control(format, 3),
};
- GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
+ GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + slot * 2], &element);
}
- if (sgvs) {
+ if (pipeline->vs_prog_data.uses_vertexid ||
+ pipeline->vs_prog_data.uses_instanceid) {
struct GEN7_VERTEX_ELEMENT_STATE element = {
.Valid = true,
/* FIXME: Do we need to provide the base vertex as component 0 here
.Component2Control = VFCOMP_STORE_VID,
.Component3Control = VFCOMP_STORE_IID
};
- GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->vertexAttributeDescriptionCount * 2], &element);
+ GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + (vb_count - 1) * 2], &element);
}
}
-static const uint32_t vk_to_gen_cullmode[] = {
- [VK_CULL_MODE_NONE] = CULLMODE_NONE,
- [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
- [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK,
- [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
-};
-
-static const uint32_t vk_to_gen_fillmode[] = {
- [VK_POLYGON_MODE_FILL] = RASTER_SOLID,
- [VK_POLYGON_MODE_LINE] = RASTER_WIREFRAME,
- [VK_POLYGON_MODE_POINT] = RASTER_POINT,
-};
-
-static const uint32_t vk_to_gen_front_face[] = {
- [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1,
- [VK_FRONT_FACE_CLOCKWISE] = 0
-};
-
static void
gen7_emit_rs_state(struct anv_pipeline *pipeline,
- const VkPipelineRasterStateCreateInfo *info,
+ const VkPipelineRasterizationStateCreateInfo *info,
const struct anv_graphics_pipeline_create_info *extra)
{
struct GEN7_3DSTATE_SF sf = {
GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
}
-static const uint32_t vk_to_gen_compare_op[] = {
- [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
- [VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
- [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
- [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
- [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
- [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
- [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
- [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
-};
-
-static const uint32_t vk_to_gen_stencil_op[] = {
- [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
- [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
- [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
- [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
- [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
- [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
- [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
- [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
-};
-
-static const uint32_t vk_to_gen_blend_op[] = {
- [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
- [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
- [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
- [VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
- [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
-};
-
-static const uint32_t vk_to_gen_logic_op[] = {
- [VK_LOGIC_OP_COPY] = LOGICOP_COPY,
- [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
- [VK_LOGIC_OP_AND] = LOGICOP_AND,
- [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
- [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
- [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
- [VK_LOGIC_OP_XOR] = LOGICOP_XOR,
- [VK_LOGIC_OP_OR] = LOGICOP_OR,
- [VK_LOGIC_OP_NOR] = LOGICOP_NOR,
- [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
- [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
- [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
- [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
- [VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
- [VK_LOGIC_OP_NAND] = LOGICOP_NAND,
- [VK_LOGIC_OP_SET] = LOGICOP_SET,
-};
-
-static const uint32_t vk_to_gen_blend[] = {
- [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
- [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
- [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
- [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
- [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
- [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
- [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR] = BLENDFACTOR_INV_CONST_COLOR,
- [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA] = BLENDFACTOR_INV_CONST_ALPHA,
- [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
- [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
- [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
-};
-
static void
gen7_emit_ds_state(struct anv_pipeline *pipeline,
const VkPipelineDepthStencilStateCreateInfo *info)
static void
gen7_emit_cb_state(struct anv_pipeline *pipeline,
- const VkPipelineColorBlendStateCreateInfo *info)
+ const VkPipelineColorBlendStateCreateInfo *info,
+ const VkPipelineMultisampleStateCreateInfo *ms_info)
{
struct anv_device *device = pipeline->device;
- uint32_t num_dwords = GEN7_BLEND_STATE_length;
- pipeline->blend_state =
- anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
-
if (info->pAttachments == NULL) {
- struct GEN7_BLEND_STATE blend_state = {
- .ColorBufferBlendEnable = false,
- .WriteDisableAlpha = false,
- .WriteDisableRed = false,
- .WriteDisableGreen = false,
- .WriteDisableBlue = false,
- };
-
- GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
+ pipeline->blend_state =
+ anv_state_pool_emit(&device->dynamic_state_pool,
+ GEN7_BLEND_STATE, 64,
+ .ColorBufferBlendEnable = false,
+ .WriteDisableAlpha = false,
+ .WriteDisableRed = false,
+ .WriteDisableGreen = false,
+ .WriteDisableBlue = false);
} else {
/* FIXME-GEN7: All render targets share blend state settings on gen7, we
* can't implement this.
*/
const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
+ pipeline->blend_state =
+ anv_state_pool_emit(&device->dynamic_state_pool,
+ GEN7_BLEND_STATE, 64,
- struct GEN7_BLEND_STATE blend_state = {
- .ColorBufferBlendEnable = a->blendEnable,
- .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
- .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
+ .ColorBufferBlendEnable = a->blendEnable,
+ .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
+ .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
- .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
- .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
+ .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
+ .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
- .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
- .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
- .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
- .AlphaToCoverageEnable = info->alphaToCoverageEnable,
+ .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
+ .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
+ .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
+ .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
# if 0
- bool AlphaToOneEnable;
- bool AlphaToCoverageDitherEnable;
+ bool AlphaToOneEnable;
+ bool AlphaToCoverageDitherEnable;
# endif
- .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
- .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
- .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
- .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
+ .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
+ .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
+ .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
+ .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
- .LogicOpEnable = info->logicOpEnable,
- .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
+ .LogicOpEnable = info->logicOpEnable,
+ .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
# if 0
- bool AlphaTestEnable;
- uint32_t AlphaTestFunction;
- bool ColorDitherEnable;
- uint32_t XDitherOffset;
- uint32_t YDitherOffset;
- uint32_t ColorClampRange;
- bool PreBlendColorClampEnable;
- bool PostBlendColorClampEnable;
+ bool AlphaTestEnable;
+ uint32_t AlphaTestFunction;
+ bool ColorDitherEnable;
+ uint32_t XDitherOffset;
+ uint32_t YDitherOffset;
+ uint32_t ColorClampRange;
+ bool PreBlendColorClampEnable;
+ bool PostBlendColorClampEnable;
# endif
- };
-
- GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
+ );
}
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
GENX_FUNC(GEN7, GEN75) VkResult
genX(graphics_pipeline_create)(
VkDevice _device,
+ struct anv_pipeline_cache * cache,
const VkGraphicsPipelineCreateInfo* pCreateInfo,
const struct anv_graphics_pipeline_create_info *extra,
+ const VkAllocationCallbacks* pAllocator,
VkPipeline* pPipeline)
{
ANV_FROM_HANDLE(anv_device, device, _device);
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
- pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
- VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
+ pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
+ VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (pipeline == NULL)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
+ result = anv_pipeline_init(pipeline, device, cache,
+ pCreateInfo, extra, pAllocator);
if (result != VK_SUCCESS) {
- anv_device_free(device, pipeline);
+ anv_free2(&device->alloc, pAllocator, pipeline);
return result;
}
assert(pCreateInfo->pVertexInputState);
- gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
+ emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
- assert(pCreateInfo->pRasterState);
- gen7_emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
+ assert(pCreateInfo->pRasterizationState);
+ gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
- gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
+ gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
+ pCreateInfo->pMultisampleState);
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
.StatisticsEnable = true);
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
- const VkPipelineRasterStateCreateInfo *rs_info = pCreateInfo->pRasterState;
+ const VkPipelineRasterizationStateCreateInfo *rs_info =
+ pCreateInfo->pRasterizationState;
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
.FrontWinding = vk_to_gen_front_face[rs_info->frontFace],
else
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
.KernelStartPointer = pipeline->vs_vec4,
- .ScratchSpaceBaseOffset = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
+ .ScratchSpaceBaseOffset = pipeline->scratch_start[MESA_SHADER_VERTEX],
.PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
.DispatchGRFStartRegisterforURBData =
const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
- if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) {
+ if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
} else {
urb_offset = 1;
urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
- .KernelStartPointer = pipeline->gs_vec4,
- .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
+ .KernelStartPointer = pipeline->gs_kernel,
+ .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
.PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
.OutputTopology = gs_prog_data->output_topology,
.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
+ .IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
.DispatchGRFStartRegisterforURBData =
gs_prog_data->base.base.dispatch_grf_start_reg,
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
.KernelStartPointer0 = pipeline->ps_ksp0,
- .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
+ .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
.PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
.MaximumNumberofThreads = device->info.max_wm_threads - 1,
GENX_FUNC(GEN7, GEN75) VkResult
genX(compute_pipeline_create)(
VkDevice _device,
+ struct anv_pipeline_cache * cache,
const VkComputePipelineCreateInfo* pCreateInfo,
+ const VkAllocationCallbacks* pAllocator,
VkPipeline* pPipeline)
{
anv_finishme("primitive_id needs sbe swizzling setup");
projects / mesa.git / blobdiff