#include "anv_private.h"
-void
-gen7_fill_buffer_surface_state(void *state, const struct anv_format *format,
- uint32_t offset, uint32_t range)
-{
- /* This assumes RGBA float format. */
-
- uint32_t stride = 16; /* Depends on whether accessing shader is simd8 or
- * vec4. Will need one of each for buffers that are
- * used in both vec4 and simd8. */
+#include "gen7_pack.h"
+#include "gen75_pack.h"
+GENX_FUNC(GEN7, GEN75) void
+genX(fill_buffer_surface_state)(void *state, const struct anv_format *format,
+ uint32_t offset, uint32_t range,
+ uint32_t stride)
+{
uint32_t num_elements = range / stride;
- struct GEN7_RENDER_SURFACE_STATE surface_state = {
+ struct GENX(RENDER_SURFACE_STATE) surface_state = {
.SurfaceType = SURFTYPE_BUFFER,
.SurfaceFormat = format->surface_format,
.SurfaceVerticalAlignment = VALIGN_4,
.SurfaceHorizontalAlignment = HALIGN_4,
.TiledSurface = false,
.RenderCacheReadWriteMode = false,
- .SurfaceObjectControlState = GEN7_MOCS,
+ .SurfaceObjectControlState = GENX(MOCS),
.Height = (num_elements >> 7) & 0x3fff,
.Width = num_elements & 0x7f,
.Depth = (num_elements >> 21) & 0x3f,
.SurfacePitch = stride - 1,
+# if (ANV_IS_HASWELL)
+ .ShaderChannelSelectR = SCS_RED,
+ .ShaderChannelSelectG = SCS_GREEN,
+ .ShaderChannelSelectB = SCS_BLUE,
+ .ShaderChannelSelectA = SCS_ALPHA,
+# endif
.SurfaceBaseAddress = { NULL, offset },
};
- GEN7_RENDER_SURFACE_STATE_pack(NULL, state, &surface_state);
-}
-
-VkResult gen7_CreateBufferView(
- VkDevice _device,
- const VkBufferViewCreateInfo* pCreateInfo,
- VkBufferView* pView)
-{
- ANV_FROM_HANDLE(anv_device, device, _device);
- struct anv_buffer_view *bview;
- VkResult result;
-
- result = anv_buffer_view_create(device, pCreateInfo, &bview);
- if (result != VK_SUCCESS)
- return result;
-
- const struct anv_format *format =
- anv_format_for_vk_format(pCreateInfo->format);
-
- gen7_fill_buffer_surface_state(bview->surface_state.map, format,
- bview->offset, pCreateInfo->range);
-
- *pView = anv_buffer_view_to_handle(bview);
-
- return VK_SUCCESS;
+ GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
}
static const uint32_t vk_to_gen_tex_filter[] = {
- [VK_TEX_FILTER_NEAREST] = MAPFILTER_NEAREST,
- [VK_TEX_FILTER_LINEAR] = MAPFILTER_LINEAR
+ [VK_FILTER_NEAREST] = MAPFILTER_NEAREST,
+ [VK_FILTER_LINEAR] = MAPFILTER_LINEAR
};
static const uint32_t vk_to_gen_mipmap_mode[] = {
- [VK_TEX_MIPMAP_MODE_BASE] = MIPFILTER_NONE,
- [VK_TEX_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
- [VK_TEX_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
+ [VK_SAMPLER_MIPMAP_MODE_BASE] = MIPFILTER_NONE,
+ [VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
+ [VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
};
static const uint32_t vk_to_gen_tex_address[] = {
- [VK_TEX_ADDRESS_MODE_WRAP] = TCM_WRAP,
- [VK_TEX_ADDRESS_MODE_MIRROR] = TCM_MIRROR,
- [VK_TEX_ADDRESS_MODE_CLAMP] = TCM_CLAMP,
- [VK_TEX_ADDRESS_MODE_MIRROR_ONCE] = TCM_MIRROR_ONCE,
- [VK_TEX_ADDRESS_MODE_CLAMP_BORDER] = TCM_CLAMP_BORDER,
+ [VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP,
+ [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
+ [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP,
+ [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
+ [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
};
static const uint32_t vk_to_gen_compare_op[] = {
[VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
[VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
[VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
- [VK_COMPARE_OP_LESS_EQUAL] = PREFILTEROPLEQUAL,
+ [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
[VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
[VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
- [VK_COMPARE_OP_GREATER_EQUAL] = PREFILTEROPGEQUAL,
+ [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
[VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
};
-VkResult gen7_CreateSampler(
+static struct anv_state
+alloc_surface_state(struct anv_device *device,
+ struct anv_cmd_buffer *cmd_buffer)
+{
+ if (cmd_buffer) {
+ return anv_cmd_buffer_alloc_surface_state(cmd_buffer);
+ } else {
+ return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
+ }
+}
+
+VkResult genX(CreateSampler)(
VkDevice _device,
const VkSamplerCreateInfo* pCreateInfo,
+ const VkAllocationCallbacks* pAllocator,
VkSampler* pSampler)
{
ANV_FROM_HANDLE(anv_device, device, _device);
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
- sampler = anv_device_alloc(device, sizeof(*sampler), 8,
- VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
+ sampler = anv_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
+ VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!sampler)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
.SamplerDisable = false,
.TextureBorderColorMode = DX10OGL,
.BaseMipLevel = 0.0,
- .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipMode],
+ .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
.MagModeFilter = mag_filter,
.MinModeFilter = min_filter,
.TextureLODBias = pCreateInfo->mipLodBias * 256,
return VK_SUCCESS;
}
-VkResult gen7_CreateDynamicRasterState(
- VkDevice _device,
- const VkDynamicRasterStateCreateInfo* pCreateInfo,
- VkDynamicRasterState* pState)
-{
- ANV_FROM_HANDLE(anv_device, device, _device);
- struct anv_dynamic_rs_state *state;
-
- assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_DYNAMIC_RASTER_STATE_CREATE_INFO);
-
- state = anv_device_alloc(device, sizeof(*state), 8,
- VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
- if (state == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
-
- bool enable_bias = pCreateInfo->depthBias != 0.0f ||
- pCreateInfo->slopeScaledDepthBias != 0.0f;
-
- struct GEN7_3DSTATE_SF sf = {
- GEN7_3DSTATE_SF_header,
- .LineWidth = pCreateInfo->lineWidth,
- .GlobalDepthOffsetEnableSolid = enable_bias,
- .GlobalDepthOffsetEnableWireframe = enable_bias,
- .GlobalDepthOffsetEnablePoint = enable_bias,
- .GlobalDepthOffsetConstant = pCreateInfo->depthBias,
- .GlobalDepthOffsetScale = pCreateInfo->slopeScaledDepthBias,
- .GlobalDepthOffsetClamp = pCreateInfo->depthBiasClamp
- };
-
- GEN7_3DSTATE_SF_pack(NULL, state->gen7.sf, &sf);
-
- *pState = anv_dynamic_rs_state_to_handle(state);
-
- return VK_SUCCESS;
-}
-
-VkResult gen7_CreateDynamicDepthStencilState(
- VkDevice _device,
- const VkDynamicDepthStencilStateCreateInfo* pCreateInfo,
- VkDynamicDepthStencilState* pState)
-{
- ANV_FROM_HANDLE(anv_device, device, _device);
- struct anv_dynamic_ds_state *state;
-
- assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_DYNAMIC_DEPTH_STENCIL_STATE_CREATE_INFO);
-
- state = anv_device_alloc(device, sizeof(*state), 8,
- VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
- if (state == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
-
- struct GEN7_DEPTH_STENCIL_STATE depth_stencil_state = {
- .StencilTestMask = pCreateInfo->stencilReadMask & 0xff,
- .StencilWriteMask = pCreateInfo->stencilWriteMask & 0xff,
- .BackfaceStencilTestMask = pCreateInfo->stencilReadMask & 0xff,
- .BackfaceStencilWriteMask = pCreateInfo->stencilWriteMask & 0xff,
- };
-
- GEN7_DEPTH_STENCIL_STATE_pack(NULL, state->gen7.depth_stencil_state,
- &depth_stencil_state);
-
- struct GEN7_COLOR_CALC_STATE color_calc_state = {
- .StencilReferenceValue = pCreateInfo->stencilFrontRef,
- .BackFaceStencilReferenceValue = pCreateInfo->stencilBackRef
- };
-
- GEN7_COLOR_CALC_STATE_pack(NULL, state->gen7.color_calc_state, &color_calc_state);
-
- *pState = anv_dynamic_ds_state_to_handle(state);
-
- return VK_SUCCESS;
-}
static const uint8_t anv_halign[] = {
[4] = HALIGN_4,
[4] = VALIGN_4,
};
-void
-gen7_image_view_init(struct anv_image_view *iview,
- struct anv_device *device,
- const VkImageViewCreateInfo* pCreateInfo,
- struct anv_cmd_buffer *cmd_buffer)
+static const uint32_t vk_to_gen_swizzle_map[] = {
+ [VK_COMPONENT_SWIZZLE_ZERO] = SCS_ZERO,
+ [VK_COMPONENT_SWIZZLE_ONE] = SCS_ONE,
+ [VK_COMPONENT_SWIZZLE_R] = SCS_RED,
+ [VK_COMPONENT_SWIZZLE_G] = SCS_GREEN,
+ [VK_COMPONENT_SWIZZLE_B] = SCS_BLUE,
+ [VK_COMPONENT_SWIZZLE_A] = SCS_ALPHA
+};
+
+static inline uint32_t
+vk_to_gen_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component)
+{
+ if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
+ return vk_to_gen_swizzle_map[component];
+ else
+ return vk_to_gen_swizzle_map[swizzle];
+}
+
+GENX_FUNC(GEN7, GEN75) void
+genX(image_view_init)(struct anv_image_view *iview,
+ struct anv_device *device,
+ const VkImageViewCreateInfo* pCreateInfo,
+ struct anv_cmd_buffer *cmd_buffer)
{
ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
+
struct anv_surface *surface =
anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
const struct anv_format *format =
anv_format_for_vk_format(pCreateInfo->format);
- const struct anv_image_view_info view_type_info =
- anv_image_view_info_for_vk_image_view_type(pCreateInfo->viewType);
-
if (pCreateInfo->viewType != VK_IMAGE_VIEW_TYPE_2D)
anv_finishme("non-2D image views");
+ iview->image = image;
iview->bo = image->bo;
iview->offset = image->offset + surface->offset;
iview->format = anv_format_for_vk_format(pCreateInfo->format);
};
uint32_t depth = 1;
- if (range->arraySize > 1) {
- depth = range->arraySize;
+ if (range->layerCount > 1) {
+ depth = range->layerCount;
} else if (image->extent.depth > 1) {
depth = image->extent.depth;
}
- struct GEN7_RENDER_SURFACE_STATE surface_state = {
- .SurfaceType = view_type_info.surface_type,
+ const struct isl_extent3d image_align_sa =
+ isl_surf_get_image_alignment_sa(&surface->isl);
+
+ struct GENX(RENDER_SURFACE_STATE) surface_state = {
+ .SurfaceType = image->surface_type,
.SurfaceArray = image->array_size > 1,
.SurfaceFormat = format->surface_format,
- .SurfaceVerticalAlignment = anv_valign[surface->v_align],
- .SurfaceHorizontalAlignment = anv_halign[surface->h_align],
+ .SurfaceVerticalAlignment = anv_valign[image_align_sa.height],
+ .SurfaceHorizontalAlignment = anv_halign[image_align_sa.width],
/* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
* Tiled Surface is False."
*/
- .TiledSurface = surface->tile_mode > LINEAR,
- .TileWalk = surface->tile_mode == YMAJOR ? TILEWALK_YMAJOR : TILEWALK_XMAJOR,
+ .TiledSurface = surface->isl.tiling != ISL_TILING_LINEAR,
+ .TileWalk = surface->isl.tiling == ISL_TILING_Y0 ?
+ TILEWALK_YMAJOR : TILEWALK_XMAJOR,
.VerticalLineStride = 0,
.VerticalLineStrideOffset = 0,
- .RenderCacheReadWriteMode = false,
+
+ .RenderCacheReadWriteMode = 0, /* TEMPLATE */
.Height = image->extent.height - 1,
.Width = image->extent.width - 1,
.Depth = depth - 1,
- .SurfacePitch = surface->stride - 1,
- .MinimumArrayElement = range->baseArraySlice,
+ .SurfacePitch = surface->isl.row_pitch - 1,
+ .MinimumArrayElement = range->baseArrayLayer,
.NumberofMultisamples = MULTISAMPLECOUNT_1,
.XOffset = 0,
.YOffset = 0,
- .SurfaceObjectControlState = GEN7_MOCS,
+ .SurfaceObjectControlState = GENX(MOCS),
- /* For render target surfaces, the hardware interprets field MIPCount/LOD as
- * LOD. The Broadwell PRM says:
- *
- * MIPCountLOD defines the LOD that will be rendered into.
- * SurfaceMinLOD is ignored.
- */
- .MIPCountLOD = range->mipLevels - 1,
- .SurfaceMinLOD = range->baseMipLevel,
+ .MIPCountLOD = 0, /* TEMPLATE */
+ .SurfaceMinLOD = 0, /* TEMPLATE */
.MCSEnable = false,
+# if (ANV_IS_HASWELL)
+ .ShaderChannelSelectR = vk_to_gen_swizzle(pCreateInfo->components.r,
+ VK_COMPONENT_SWIZZLE_R),
+ .ShaderChannelSelectG = vk_to_gen_swizzle(pCreateInfo->components.g,
+ VK_COMPONENT_SWIZZLE_G),
+ .ShaderChannelSelectB = vk_to_gen_swizzle(pCreateInfo->components.b,
+ VK_COMPONENT_SWIZZLE_B),
+ .ShaderChannelSelectA = vk_to_gen_swizzle(pCreateInfo->components.a,
+ VK_COMPONENT_SWIZZLE_A),
+# else /* XXX: Seriously? */
.RedClearColor = 0,
.GreenClearColor = 0,
.BlueClearColor = 0,
.AlphaClearColor = 0,
+# endif
.ResourceMinLOD = 0.0,
.SurfaceBaseAddress = { NULL, iview->offset },
};
- if (cmd_buffer) {
- iview->surface_state =
- anv_state_stream_alloc(&cmd_buffer->surface_state_stream, 64, 64);
- } else {
- iview->surface_state =
- anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
- }
-
- GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->surface_state.map,
- &surface_state);
-}
-
-void
-gen7_color_attachment_view_init(struct anv_attachment_view *aview,
- struct anv_device *device,
- const VkAttachmentViewCreateInfo* pCreateInfo,
- struct anv_cmd_buffer *cmd_buffer)
-{
- ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
- struct anv_image_view *iview = &aview->image_view;
- struct anv_surface *surface =
- anv_image_get_surface_for_color_attachment(image);
-
- aview->attachment_type = ANV_ATTACHMENT_VIEW_TYPE_COLOR;
-
- anv_assert(pCreateInfo->arraySize > 0);
- anv_assert(pCreateInfo->mipLevel < image->levels);
- anv_assert(pCreateInfo->baseArraySlice + pCreateInfo->arraySize <= image->array_size);
+ if (image->needs_nonrt_surface_state) {
+ iview->nonrt_surface_state = alloc_surface_state(device, cmd_buffer);
- iview->bo = image->bo;
- iview->offset = image->offset + surface->offset;
- iview->format = anv_format_for_vk_format(pCreateInfo->format);
+ surface_state.RenderCacheReadWriteMode = false;
- iview->extent = (VkExtent3D) {
- .width = anv_minify(image->extent.width, pCreateInfo->mipLevel),
- .height = anv_minify(image->extent.height, pCreateInfo->mipLevel),
- .depth = anv_minify(image->extent.depth, pCreateInfo->mipLevel),
- };
+ /* For non render target surfaces, the hardware interprets field
+ * MIPCount/LOD as MIPCount. The range of levels accessible by the
+ * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
+ */
+ surface_state.SurfaceMinLOD = range->baseMipLevel;
+ surface_state.MIPCountLOD = range->levelCount - 1;
- uint32_t depth = 1;
- if (pCreateInfo->arraySize > 1) {
- depth = pCreateInfo->arraySize;
- } else if (image->extent.depth > 1) {
- depth = image->extent.depth;
- }
+ GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->nonrt_surface_state.map,
+ &surface_state);
- if (cmd_buffer) {
- iview->surface_state =
- anv_state_stream_alloc(&cmd_buffer->surface_state_stream, 64, 64);
- } else {
- iview->surface_state =
- anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
+ if (!device->info.has_llc)
+ anv_state_clflush(iview->nonrt_surface_state);
}
- struct GEN7_RENDER_SURFACE_STATE surface_state = {
- .SurfaceType = SURFTYPE_2D,
- .SurfaceArray = image->array_size > 1,
- .SurfaceFormat = iview->format->surface_format,
- .SurfaceVerticalAlignment = anv_valign[surface->v_align],
- .SurfaceHorizontalAlignment = anv_halign[surface->h_align],
-
- /* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
- * Tiled Surface is False."
- */
- .TiledSurface = surface->tile_mode > LINEAR,
- .TileWalk = surface->tile_mode == YMAJOR ? TILEWALK_YMAJOR : TILEWALK_XMAJOR,
-
- .VerticalLineStride = 0,
- .VerticalLineStrideOffset = 0,
- .RenderCacheReadWriteMode = WriteOnlyCache,
-
- .Height = image->extent.height - 1,
- .Width = image->extent.width - 1,
- .Depth = depth - 1,
- .SurfacePitch = surface->stride - 1,
- .MinimumArrayElement = pCreateInfo->baseArraySlice,
- .NumberofMultisamples = MULTISAMPLECOUNT_1,
- .XOffset = 0,
- .YOffset = 0,
+ if (image->needs_color_rt_surface_state) {
+ iview->color_rt_surface_state = alloc_surface_state(device, cmd_buffer);
- .SurfaceObjectControlState = GEN7_MOCS,
+ surface_state.RenderCacheReadWriteMode = 0; /* Write only */
/* For render target surfaces, the hardware interprets field MIPCount/LOD as
* LOD. The Broadwell PRM says:
* MIPCountLOD defines the LOD that will be rendered into.
* SurfaceMinLOD is ignored.
*/
- .SurfaceMinLOD = 0,
- .MIPCountLOD = pCreateInfo->mipLevel,
+ surface_state.MIPCountLOD = range->baseMipLevel;
+ surface_state.SurfaceMinLOD = 0;
- .MCSEnable = false,
- .RedClearColor = 0,
- .GreenClearColor = 0,
- .BlueClearColor = 0,
- .AlphaClearColor = 0,
- .ResourceMinLOD = 0.0,
- .SurfaceBaseAddress = { NULL, iview->offset },
+ GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->color_rt_surface_state.map,
+ &surface_state);
+ if (!device->info.has_llc)
+ anv_state_clflush(iview->color_rt_surface_state);
+ }
- };
+ if (image->needs_storage_surface_state) {
+ iview->storage_surface_state = alloc_surface_state(device, cmd_buffer);
- GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->surface_state.map,
- &surface_state);
+ surface_state.SurfaceFormat =
+ isl_lower_storage_image_format(&device->isl_dev,
+ format->surface_format);
+
+ surface_state.SurfaceMinLOD = range->baseMipLevel;
+ surface_state.MIPCountLOD = range->levelCount - 1;
+
+ GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->storage_surface_state.map,
+ &surface_state);
+ }
}
projects / mesa.git / blobdiff