#include "gen8_pack.h"
#include "gen9_pack.h"
+#include "genX_pipeline_util.h"
+
static void
emit_vertex_input(struct anv_pipeline *pipeline,
- const VkPipelineVertexInputStateCreateInfo *info)
+ const VkPipelineVertexInputStateCreateInfo *info,
+ const struct anv_graphics_pipeline_create_info *extra)
{
- const uint32_t num_dwords = 1 + info->vertexAttributeDescriptionCount * 2;
- uint32_t *p;
-
static_assert(ANV_GEN >= 8, "should be compiling this for gen < 8");
- if (info->vertexAttributeDescriptionCount > 0) {
+ uint32_t elements;
+ if (extra && extra->disable_vs) {
+ /* If the VS is disabled, just assume the user knows what they're
+ * doing and apply the layout blindly. This can only come from
+ * meta, so this *should* be safe.
+ */
+ elements = 0;
+ for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
+ elements |= (1 << info->pVertexAttributeDescriptions[i].location);
+ } else {
+ /* Pull inputs_read out of the VS prog data */
+ uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
+ assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
+ elements = inputs_read >> VERT_ATTRIB_GENERIC0;
+ }
+
+ const uint32_t num_dwords = 1 + __builtin_popcount(elements) * 2;
+
+ uint32_t *p;
+ if (elements != 0) {
p = anv_batch_emitn(&pipeline->batch, num_dwords,
GENX(3DSTATE_VERTEX_ELEMENTS));
+ memset(p + 1, 0, (num_dwords - 1) * 4);
}
for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
const VkVertexInputAttributeDescription *desc =
&info->pVertexAttributeDescriptions[i];
- const struct anv_format *format = anv_format_for_vk_format(desc->format);
+ enum isl_format format = anv_get_isl_format(desc->format,
+ VK_IMAGE_ASPECT_COLOR_BIT,
+ VK_IMAGE_TILING_LINEAR);
+
+ assert(desc->binding < 32);
+
+ if ((elements & (1 << desc->location)) == 0)
+ continue; /* Binding unused */
+
+ uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
struct GENX(VERTEX_ELEMENT_STATE) element = {
.VertexBufferIndex = desc->binding,
.Valid = true,
- .SourceElementFormat = format->surface_format,
+ .SourceElementFormat = format,
.EdgeFlagEnable = false,
.SourceElementOffset = desc->offset,
- .Component0Control = VFCOMP_STORE_SRC,
- .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
+ .Component0Control = vertex_element_comp_control(format, 0),
+ .Component1Control = vertex_element_comp_control(format, 1),
+ .Component2Control = vertex_element_comp_control(format, 2),
+ .Component3Control = vertex_element_comp_control(format, 3),
};
- GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
+ GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
.InstancingEnable = pipeline->instancing_enable[desc->binding],
- .VertexElementIndex = i,
+ .VertexElementIndex = slot,
/* Vulkan so far doesn't have an instance divisor, so
* this is always 1 (ignored if not instancing). */
.InstanceDataStepRate = 1);
}
+ const uint32_t id_slot = __builtin_popcount(elements);
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
.VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
.VertexIDComponentNumber = 2,
- .VertexIDElementOffset = info->vertexBindingDescriptionCount,
+ .VertexIDElementOffset = id_slot,
.InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
.InstanceIDComponentNumber = 3,
- .InstanceIDElementOffset = info->vertexBindingDescriptionCount);
+ .InstanceIDElementOffset = id_slot);
}
static void
const VkPipelineRasterizationStateCreateInfo *info,
const struct anv_graphics_pipeline_create_info *extra)
{
- static const uint32_t vk_to_gen_cullmode[] = {
- [VK_CULL_MODE_NONE] = CULLMODE_NONE,
- [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
- [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK,
- [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
- };
-
- static const uint32_t vk_to_gen_fillmode[] = {
- [VK_POLYGON_MODE_FILL] = RASTER_SOLID,
- [VK_POLYGON_MODE_LINE] = RASTER_WIREFRAME,
- [VK_POLYGON_MODE_POINT] = RASTER_POINT,
- };
-
- static const uint32_t vk_to_gen_front_face[] = {
- [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1,
- [VK_FRONT_FACE_CLOCKWISE] = 0
- };
-
struct GENX(3DSTATE_SF) sf = {
GENX(3DSTATE_SF_header),
.ViewportTransformEnable = !(extra && extra->disable_viewport),
.BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
.ScissorRectangleEnable = !(extra && extra->disable_scissor),
#if ANV_GEN == 8
- .ViewportZClipTestEnable = info->depthClipEnable
+ .ViewportZClipTestEnable = true,
#else
/* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
- .ViewportZFarClipTestEnable = info->depthClipEnable,
- .ViewportZNearClipTestEnable = info->depthClipEnable,
+ .ViewportZFarClipTestEnable = true,
+ .ViewportZNearClipTestEnable = true,
#endif
};
{
struct anv_device *device = pipeline->device;
- static const uint32_t vk_to_gen_logic_op[] = {
- [VK_LOGIC_OP_COPY] = LOGICOP_COPY,
- [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
- [VK_LOGIC_OP_AND] = LOGICOP_AND,
- [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
- [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
- [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
- [VK_LOGIC_OP_XOR] = LOGICOP_XOR,
- [VK_LOGIC_OP_OR] = LOGICOP_OR,
- [VK_LOGIC_OP_NOR] = LOGICOP_NOR,
- [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
- [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
- [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
- [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
- [VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
- [VK_LOGIC_OP_NAND] = LOGICOP_NAND,
- [VK_LOGIC_OP_SET] = LOGICOP_SET,
- };
-
- static const uint32_t vk_to_gen_blend[] = {
- [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
- [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
- [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
- [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
- [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
- [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
- [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
- [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
- [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
- [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
- [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
- [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
- };
-
- static const uint32_t vk_to_gen_blend_op[] = {
- [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
- [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
- [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
- [VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
- [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
- };
-
uint32_t num_dwords = GENX(BLEND_STATE_length);
pipeline->blend_state =
anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
}
GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
+ if (!device->info.has_llc)
+ anv_state_clflush(pipeline->blend_state);
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
.BlendStatePointer = pipeline->blend_state.offset,
.BlendStatePointerValid = true);
}
-static const uint32_t vk_to_gen_compare_op[] = {
- [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
- [VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
- [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
- [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
- [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
- [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
- [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
- [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
-};
-
-static const uint32_t vk_to_gen_stencil_op[] = {
- [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
- [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
- [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
- [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
- [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
- [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
- [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
- [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
-};
-
static void
emit_ds_state(struct anv_pipeline *pipeline,
const VkPipelineDepthStencilStateCreateInfo *info)
VkResult
genX(graphics_pipeline_create)(
VkDevice _device,
+ struct anv_pipeline_cache * cache,
const VkGraphicsPipelineCreateInfo* pCreateInfo,
const struct anv_graphics_pipeline_create_info *extra,
const VkAllocationCallbacks* pAllocator,
if (pipeline == NULL)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
- if (result != VK_SUCCESS)
+ result = anv_pipeline_init(pipeline, device, cache,
+ pCreateInfo, extra, pAllocator);
+ if (result != VK_SUCCESS) {
+ anv_free2(&device->alloc, pAllocator, pipeline);
return result;
-
- /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
- * hard code this to num_attributes - 2. This is because the attributes
- * include VUE header and position, which aren't counted as varying
- * inputs. */
- if (pipeline->vs_simd8 == NO_KERNEL) {
- pipeline->wm_prog_data.num_varying_inputs =
- pCreateInfo->pVertexInputState->vertexAttributeDescriptionCount - 2;
}
assert(pCreateInfo->pVertexInputState);
- emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
+ emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
assert(pCreateInfo->pInputAssemblyState);
emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
assert(pCreateInfo->pRasterizationState);
offset = 1;
length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
- if (pipeline->gs_vec4 == NO_KERNEL)
+ if (pipeline->gs_kernel == NO_KERNEL)
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
else
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
.SingleProgramFlow = false,
- .KernelStartPointer = pipeline->gs_vec4,
+ .KernelStartPointer = pipeline->gs_kernel,
.VectorMaskEnable = Dmask,
.SamplerCount = 0,
.BindingTableEntryCount = 0,
.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
.OutputTopology = gs_prog_data->output_topology,
.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
+ .IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
.DispatchGRFStartRegisterForURBData =
gs_prog_data->base.base.dispatch_grf_start_reg,
offset = 1;
length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
- if (pipeline->vs_simd8 == NO_KERNEL || (extra && extra->disable_vs))
+ uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
+ pipeline->vs_vec4;
+
+ if (vs_start == NO_KERNEL || (extra && extra->disable_vs))
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
.FunctionEnable = false,
/* Even if VS is disabled, SBE still gets the amount of
.VertexURBEntryOutputLength = length);
else
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
- .KernelStartPointer = pipeline->vs_simd8,
+ .KernelStartPointer = vs_start,
.SingleVertexDispatch = Multiple,
.VectorMaskEnable = Dmask,
.SamplerCount = 0,
.MaximumNumberofThreads = device->info.max_vs_threads - 1,
.StatisticsEnable = false,
- .SIMD8DispatchEnable = true,
+ .SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL,
.VertexCacheDisable = false,
.FunctionEnable = true,
* shared with other gens.
*/
const struct brw_vue_map *fs_input_map;
- if (pipeline->gs_vec4 == NO_KERNEL)
+ if (pipeline->gs_kernel == NO_KERNEL)
fs_input_map = &vue_prog_data->vue_map;
else
fs_input_map = &gs_prog_data->base.vue_map;
if (input_index < 0)
continue;
- /* We have to subtract two slots to accout for the URB entry output
- * read offset in the VS and GS stages.
- */
- int source_attr = fs_input_map->varying_to_slot[attr] - 2;
+ int source_attr = fs_input_map->varying_to_slot[attr];
max_source_attr = MAX2(max_source_attr, source_attr);
if (input_index >= 16)
continue;
- swiz.Attribute[input_index].SourceAttribute = source_attr;
+ if (source_attr == -1) {
+ /* This attribute does not exist in the VUE--that means that the
+ * vertex shader did not write to it. It could be that it's a
+ * regular varying read by the fragment shader but not written by the
+ * vertex shader or it's gl_PrimitiveID. In the first case the value
+ * is undefined, in the second it needs to be gl_PrimitiveID.
+ */
+ swiz.Attribute[input_index].ConstantSource = PRIM_ID;
+ swiz.Attribute[input_index].ComponentOverrideX = true;
+ swiz.Attribute[input_index].ComponentOverrideY = true;
+ swiz.Attribute[input_index].ComponentOverrideZ = true;
+ swiz.Attribute[input_index].ComponentOverrideW = true;
+ } else {
+ /* We have to subtract two slots to accout for the URB entry output
+ * read offset in the VS and GS stages.
+ */
+ swiz.Attribute[input_index].SourceAttribute = source_attr - 2;
+ }
}
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
VkResult genX(compute_pipeline_create)(
VkDevice _device,
+ struct anv_pipeline_cache * cache,
const VkComputePipelineCreateInfo* pCreateInfo,
const VkAllocationCallbacks* pAllocator,
VkPipeline* pPipeline)
pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
pipeline->batch.relocs = &pipeline->batch_relocs;
- anv_state_stream_init(&pipeline->program_stream,
- &device->instruction_block_pool);
-
/* When we free the pipeline, we detect stages based on the NULL status
* of various prog_data pointers. Make them NULL by default.
*/
pipeline->vs_simd8 = NO_KERNEL;
pipeline->vs_vec4 = NO_KERNEL;
- pipeline->gs_vec4 = NO_KERNEL;
+ pipeline->gs_kernel = NO_KERNEL;
pipeline->active_stages = 0;
pipeline->total_scratch = 0;
assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
- anv_pipeline_compile_cs(pipeline, pCreateInfo, module,
+ anv_pipeline_compile_cs(pipeline, cache, pCreateInfo, module,
pCreateInfo->stage.pName);
pipeline->use_repclear = false;
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