const VkVertexInputAttributeDescription *desc =
&info->pVertexAttributeDescriptions[i];
enum isl_format format = anv_get_isl_format(desc->format,
- VK_IMAGE_ASPECT_COLOR_BIT);
+ VK_IMAGE_ASPECT_COLOR_BIT,
+ VK_IMAGE_TILING_LINEAR);
assert(desc->binding < 32);
VkResult
genX(graphics_pipeline_create)(
VkDevice _device,
+ struct anv_pipeline_cache * cache,
const VkGraphicsPipelineCreateInfo* pCreateInfo,
const struct anv_graphics_pipeline_create_info *extra,
const VkAllocationCallbacks* pAllocator,
if (pipeline == NULL)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
- if (result != VK_SUCCESS)
+ result = anv_pipeline_init(pipeline, device, cache,
+ pCreateInfo, extra, pAllocator);
+ if (result != VK_SUCCESS) {
+ anv_free2(&device->alloc, pAllocator, pipeline);
return result;
+ }
assert(pCreateInfo->pVertexInputState);
emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
if (input_index < 0)
continue;
- /* We have to subtract two slots to accout for the URB entry output
- * read offset in the VS and GS stages.
- */
- int source_attr = fs_input_map->varying_to_slot[attr] - 2;
+ int source_attr = fs_input_map->varying_to_slot[attr];
max_source_attr = MAX2(max_source_attr, source_attr);
if (input_index >= 16)
continue;
- swiz.Attribute[input_index].SourceAttribute = source_attr;
+ if (source_attr == -1) {
+ /* This attribute does not exist in the VUE--that means that the
+ * vertex shader did not write to it. It could be that it's a
+ * regular varying read by the fragment shader but not written by the
+ * vertex shader or it's gl_PrimitiveID. In the first case the value
+ * is undefined, in the second it needs to be gl_PrimitiveID.
+ */
+ swiz.Attribute[input_index].ConstantSource = PRIM_ID;
+ swiz.Attribute[input_index].ComponentOverrideX = true;
+ swiz.Attribute[input_index].ComponentOverrideY = true;
+ swiz.Attribute[input_index].ComponentOverrideZ = true;
+ swiz.Attribute[input_index].ComponentOverrideW = true;
+ } else {
+ /* We have to subtract two slots to accout for the URB entry output
+ * read offset in the VS and GS stages.
+ */
+ swiz.Attribute[input_index].SourceAttribute = source_attr - 2;
+ }
}
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
VkResult genX(compute_pipeline_create)(
VkDevice _device,
+ struct anv_pipeline_cache * cache,
const VkComputePipelineCreateInfo* pCreateInfo,
const VkAllocationCallbacks* pAllocator,
VkPipeline* pPipeline)
pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
pipeline->batch.relocs = &pipeline->batch_relocs;
- anv_state_stream_init(&pipeline->program_stream,
- &device->instruction_block_pool);
-
/* When we free the pipeline, we detect stages based on the NULL status
* of various prog_data pointers. Make them NULL by default.
*/
assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
- anv_pipeline_compile_cs(pipeline, pCreateInfo, module,
+ anv_pipeline_compile_cs(pipeline, cache, pCreateInfo, module,
pCreateInfo->stage.pName);
pipeline->use_repclear = false;