clarify summary

[libreriscv.git] / svp64-primer / acronyms.tex

diff --git a/svp64-primer/acronyms.tex b/svp64-primer/acronyms.tex
index ad6a59d8f1cc7dbd6559e1b6a93deaf15ce313f2..99d84855479f2d3482636c6c4daad673268c5645 100644 (file)
--- a/svp64-primer/acronyms.tex
+++ b/svp64-primer/acronyms.tex
@@ -1,11 +1,21 @@
 \section{List of Acronyms}
 \begin{acronym}
+       \acro{ASIC}{Application Specific Integrated Circuit}
+       \acro{AVX-512}{Intel Advanced Vector Extensions 512-bit}
        \acro{CPU}{Central Processing Unit}
-       \acro{ISA}{Instruction Set Architecture}
-       \acro{DAXPY}{double-precision aX plus Y}
        \acro{DCT}{Discrete Cosine Transform}
+       \acro{DSP}{Digital Signal Processors}
+       \acro{DAXPY}{Double-Precision aX Plus Y ($aX+Y$)}
        \acro{FFT}{Fast Fourier Transform}
+       \acro{IA-32}{Intel Architecture 32-bit or i386}
+       \acro{ISA}{Instruction Set Architecture}
+       \acro{MMX}{Intel's first SIMD implementation}
+       \acro{RVV}{RISC-V Vector extension}
        \acro{SIMD}{Single Instruction Multiple Data}
-       \acro{SV}{(Scalable) Simple Vectorisation}
+       \acro{SWAR}{SIMD Within A Register (see Flynn's Taxonomy)}
+       \acro{SV}{(Scalable) Simple Vectorisation or Simple-V}
+       \acro{SVE2}{ARM Scalable Vector Extension version two}
        \acro{SVP64}{Simple-V with Prefixing of Power ISA, 64-bits in length}
+       \acro{VLIW}{Very Long Instruction Word}
+       \acro{VSX}{128-bit Packed SIMD Extension to the Power ISA}
 \end{acronym}